Mikael Björk

Toward Nanowire Electronics

This paper discusses the electronic transport properties of nanowire field-effect transistors (NW-FETs). Four different device concepts are studied in detail: Schottky-barrier NW-FETs with metallic source and drain contacts, conventional-type NW-FETs with doped NW segments as source and drain electrodes, and, finally, two new concepts that enable steep turn-on characteristics, namely, NW impact ionization FETs and tunnel NW-FETs. As it turns out, NW-FETs are, to a large extent, determined by the device geometry, the dimensionality of the electronic transport, and the way of making contacts to the NW. Analytical as well as simulation results are compared with experimental data to explain the various factors impacting the electronic transport in NW-FETs.

Donor deactivation in silicon nanostructures

The operation of electronic devices relies on the density of free charge carriers available in the semiconductor; in most semiconductor devices this density is controlled by the addition of doping atoms. As dimensions are scaled down to achieve economic and performance benefits, the presence of interfaces and materials adjacent to the semiconductor will become more important and will eventually completely determine the electronic properties of the device. To sustain further improvements in performance, novel field-effect transistor architectures, such as FinFETs and nanowire field-effect transistors, have been proposed as replacements for the planar devices used today, and also for applications in biosensing and power generation. The successful operation of such devices will depend on our ability to precisely control the location and number of active impurity atoms in the host semiconductor during the fabrication process. Here, we demonstrate that the free carrier density in semiconductor nanowires is dependent on the size of the nanowires. By measuring the electrical conduction of doped silicon nanowires as a function of nanowire radius, temperature and dielectric surrounding, we show that the donor ionization energy increases with decreasing nanowire radius, and that it profoundly modifies the attainable free carrier density at values of the radius much larger than those at which quantum and dopant surface segregation effects set in. At a nanowire radius of 15 nm the carrier density is already 50% lower than in bulk silicon due to the dielectric mismatch between the conducting channel and its surroundings.

Silicon nanowire tunneling field-effect transistors

We demonstrate the implementation of tunneling field-effect transistors (TFETs) based on silicon nanowires (NWs) that were grown using the vapor-liquid-solid growth method. The Si NWs contain p-i-n+ segments that were achieved by in situ doping using phosphine and diborane as the n- and p-type dopant source, respectively. Electrical measurements of the TFETs show a band-to-band tunneling branch in the transfer characteristics. Furthermore, an increase in the on-state current and a decrease in the inverse subthreshold slope upon reducing the gate oxide thickness are measured. This matches theoretical calculations using a Wenzel Kramer Brillouin approximation with nanowire diameter and oxide thickness as input parameters.

Growth and characterization of GaAs and InAs nano-whiskers and InAs/GaAs heterostructures

Semiconducting InAs and GaAs nano-whiskers have been grown using a chemical beam epitaxy approach in combination with size-selected catalytic Au aerosol particles. The characterization of InAs and GaAs whiskers shows high crystalline quality as seen by transmission electron microscopy. Gate-dependent transport measurements suggests a diffusive electronic transport mechanism. We have also combined these two material systems by growing a very abrupt heterostructure interface within the whiskers, allowing the growth of highly mismatched structures without misfit dislocations

Sulfur passivation for ohmic contact formation to InAs nanowires

We have studied the formation of ohmic contacts to InAs nanowires by chemical etching and passivation of the contact areas in an ammonium polysulfide, (NH4)2Sx, water solution. The nanowires were exposed to different dilution levels of the (NH4)2Sx solution before contact metal evaporation. A process based on a highly diluted (NH4)2Sx solution was found to be self-terminating, with minimal etching of the InAs. The stability of the contacts was investigated with electrical measurements as a function of storage time in vacuum and air.

Vertical surround-gated silicon nanowire impact ionization field-effect transistors

One of the fundamental limits in the scaling of metal oxide semiconductor field-effect transistor technology is the room-temperature (RT) limit of ∼60mV/decade in the inverse subthreshold slope. Here, the authors demonstrate vertical integration of a single surround-gated silicon nanowire field-effect transistor with an inverse subthreshold slope as low as 6mV/decade at RT that spans four orders of magnitude in current. Operation of the device is based on avalanche breakdown in a partially gated vertical nanowire, epitaxially grown using the vapor-liquid-solid method. Low-power logic based on impact ionization field-effect transistors in combination with a vertical architecture is very promising for future high-performance ultrahigh-density circuits.

Si–InAs heterojunction Esaki tunnel diodes with high current densities

Si–InAs heterojunction p-n diodes were fabricated by growing InAs nanowires in oxide mask openings on silicon substrates. At substrate doping concentrations of 1×1016 and 1×1019 cm−3, conventional diode characteristics were obtained, from which a valence band offset between Si and InAs of 130 meV was extracted. For a substrate doping of 4×1019 cm−3, heterojunction tunnel diode characteristics were obtained showing current densities in the range of 50 kA/cm2 at 0.5 V reverse bias. In addition, in situ doping of the InAs wires was performed using disilane to further boost the tunnel currents up to 100 kA/cm2 at 0.5 V reverse bias for the highest doping ratios.

Tuning the Light Emission from GaAs Nanowires over 290 meV with Uniaxial Strain

Strain engineering has been used to increase the charge carrier mobility of complementary metal-oxide-semiconductor transistors as well as to boost and tune the performance of optoelectronic devices, enabling wavelength tuning, polarization selectivity and suppression of temperature drifts. Semiconducting nanowires benefit from enhanced mechanical properties, such as increased yield strength, that turn out to be beneficial to amplify strain effects. Here we use photoluminescence (PL) to study the effect of uniaxial stress on the electronic properties of GaAs/Al0.3Ga0.7As/GaAs core/shell nanowires. Both compressive and tensile mechanical stress were applied continuously and reversibly to the nanowire, resulting in a remarkable decrease of the bandgap of up to 296 meV at 3.5% of strain. Raman spectra were measured and analyzed to determine the axial strain in the nanowire and the Poisson ratio in the <111> direction. In both PL and Raman spectra, we observe fingerprints of symmetry breaking due to anisotropic deformation of the nanowire. The shifts observed in the PL and Raman spectra are well described by bulk deformation potentials for band structure and phonon energies. The fact that exceptionally high elastic strain can be applied to semiconducting nanowires makes them ideally suited for novel device applications that require a tuning of the band structure over a broad range.

Trap-assisted tunneling in Si-InAs nanowire heterojunction tunnel diodes.

We report on the electrical characterization of one-sided p(+)-si/n-InAs nanowire heterojunction tunnel diodes to provide insight into the tunnel process occurring in this highly lattice mismatched material system. The lattice mismatch gives rise to dislocations at the interface as confirmed by electron microscopy. Despite this, a negative differential resistance with peak-to-valley current ratios of up to 2.4 at room temperature and with large current densities is observed, attesting to the very abrupt and high-quality interface. The presence of dislocations and other defects that increase the excess current is evident in the first and second derivative of the I-V characteristics as distinct peaks arising from trap-and phonon-assisted tunneling via the corresponding defect levels. We observe this assisted tunneling mainly in the forward direction and at low reverse bias but not at higher reverse biases because the band-to-band generation rates are peaked in the InAs, which is also confirmed by modeling. This indicates that most of the peaks are due to dislocations and defects in the immediate vicinity of the interface. Finally, we also demonstrate that these devices are very sensitive to electrical stress, in particular at room temperature, because of the extremely high electrical fields obtained at the abrupt junction even at low bias. The electrical stress induces additional defect levels in the band gap, which reduce the peak-to-valley current ratios.

Patterned epitaxial vapor-liquid-solid growth of silicon nanowires on Si(111) using silane

We have carried out a detailed study on the vapour-liquid-solid growth of silicon nanowires (SiNWs) on (111)-oriented Si substrates using Au as catalytic seed material. Arrays of individual seeds were patterned by electron-beam lithography, followed by Au evaporation and lift-off. SiNWs were grown using diluted silane as precursor gas in a low-pressure chemical vapor deposition system. The silane partial pressure, substrate temperature, and seed diameter were systematically varied to obtain the growth rate of the NWs and the rate of sidewall deposition. Activation energies of 19kcal∕mol for the axial SiNW growth and 29kcal∕mol for the radial deposition on the SiNW surface are derived from the data. SiNW growth at elevated temperatures is accompanied by significant Au surface diffusion, leading to a loss of Au from the tips of the SiNWs that depends on the layout and density of the Au seeds patterned. In contrast to NWs grown from a thin-film-nucleated substrate, the deterministic patterning of identical A...