Mike Tripp

Elimination of traditional functional testing of interface timings at intel

This work summarizes the design for test (DFT) circuitry and test methods that enabled Intel to shift away from traditional functional testing of I/Os. This shift was one of the key enablers for automatic test equipment (ATE) re-use and the move to lower capability (& cost) structural test platforms. Specific examples include circuit implementations from the Pentium/sup /spl reg// 4 processor, high volume manufacturing (HVM) data, and evolutionary changes to address key learnings. We close with indications of how this can be extended to cover the next generation high speed serial like interfaces.

Realizing the benefits of structural test for Intel microprocessors

This paper traces the evolution of the distributed test strategy at Intel, covering both the tester platform, which is now on the 2nd generation, as well as the parallel evolution of the test content, which is optimized for this platform. We describe the distribution of Pentium/spl reg/ 4 processor test content between structural and functional platforms, associated fallout, and key issues encountered with content migration. Finally, we discuss future test content and platform trends as shaped by increasing device complexity and defect types.

The Challenges of Nanotechnology and Gigacomplexity

In his keynote address at the 2007 International Test Conference, Gadi Singer (vice president of the Mobility Group and general manager of the SOC Enabling Group at Intel) provided Intels perspective on evolving computing trends, continuing and future challenges of nanoscale device integration, the resulting gigascale complexity, and the implications of all this for test.

Design considerations and DFT to enable testing of digital interfaces

In the last 15 years, the specifications for digital interfaces have evolved significantly, from specifying only nominal or typical values to specifying extreme maximum or minimum values that are observable at the pins of the device to values that are not directly observable at the pins of the device. There has been a corresponding evolution of high volume manufacturing (HVM) testing methods. This tutorial paper summarizes the various digital interfaces specifications, the techniques used to test then, and the associated design considerations and design for test (DFT) circuitry. The example specifications and test data are from my experience on Intel Pentium-Pro, Pentium III and Pentium 4 microprocessors.

On-die DFT based solutions are sufficient for testing multi-GHz interfaces in manufacturing (and are also key to enabling lower cost ATE platforms)

Based on experiences with 500 MHz to 1 GHz interfaces on high volume CPU and chipset products, it is evident that on-die DFT based solutions are sufficient to screen defects in manufacturing. On-die DFT and test methods can very accurately determine differences in performance (drive, timing, leakage, jitter,...) between the various interface channels on a single device, and the magnitude of the difference can be used as indication of defective channels.

ITC 2004 panel: cost of test - taking control Mike Tripp Intel Corporation

At Intel we are very focused on the Cost of Test, but we try to keep it in the proper context and focus on the Cost of Quality. By working with our customers, our Quality and Reliability group establishes required quality metrics for our products and the process steps to monitor outgoing quality. The quality goals are used to drive the test process as a whole and we optimize the steps within the process to minimize cost to Intel. For example, we optimize the content at wafer sort to achieve cost effective packaging yields (note this is NOT ppm level screening), provide feedback to the fab, and provide information to allow process optimization post packaging (for example, optimizing Burn-In). We start with fairly exhaustive flows and content and then quickly minimize them base on manufacturing data (like eliminating extra test sockets, conditions or noneffective or redundant patterns).