Min-hyung Cho

A 105.5 dB, 0.49 mm 2 Audio ΣΔ modulator using chopper stabilization and fully randomized DWA

An audio S.modulator achieves 105.5 dB dynamic range over 20 kHz audio bandwidth. A chopper stabilization technique is used in both the first integrator and the reference buffer to prevent degradation of the dynamic range and the peak signal-to-noise-plus-distortion-ratio due to flicker noise. A fully randomized data weighted averaging is used as a dynamic element matching technique to suppress the generation of spurious tones with a negligible increase in the in-band noise compared to conventional data weighted averaging. The chip was fabricated in 0.13 mum CMOS technology (I/O devices) and occupies a small chip area of 0.49 mm2. The total power consumption is 9.9 mW from a 3.3 V supply.

A 1 V 6-bit 2.4 GS/s Nyquist CMOS DAC for UWB systems

A 6-bit 2.4 GS/s current-steering DAC fabricated in a 65 nm CMOS technology for ultra-wideband (UWB) systems is presented. The prototype achieves a measured spurious-free dynamic range (SFDR) of more than 36 dB over the Nyquist bandwidth at 2.4 GS/s. Among the 50 measured samples, DNL/INL of 0.02/0.02 LSB was the lowest achievable value. The DAC core occupies an area of merely 0.023 mm2 through simplified circuit and careful layout. To operate from a relatively low analog power supply of 1 V, a portion of current cell is implemented using low threshold voltage devices. Total maximum power consumption, including the low voltage differential signaling (LVDS) stage, is 14 mW at 2.4 GS/s.