Tae Moon Roh

High-voltage power integrated circuit technology using SOI for driving plasma display panels

A new high-voltage (HV) power IC technology using high-performance p-LDMOS transistors and an excellent dielectric isolation technology has been proposed to apply the scan driver of color plasma display panel (C-PDP) system. This novel technique reduces over 40 process steps and results in smaller chip size area of the developed scan driver than that of conventional driver using conventional power IC technology. The chip size and the rise time of the PDP scan driver IC developed by this technology could be reduced by 35% and 60%, respectively, compared with the conventional design.

A novel simplified process for fabricating a very high density p-channel trench gate power MOSFET

A novel simplified fabrication method of a very high density p-channel trench gate power MOSFET using four mask layers and nitride/TEOS sidewall spacers is realized. The proposed process showed improved on-resistance characteristics of the device with increasing cell density and the cost-effective production capability due to the lesser number of processing steps. By using this process technique, a remarkably increased high density (100 Mcell/inch/sup 2/) trench gate power MOSFET with a cell pitch of 2.5 /spl mu/m could be effectively realized. The fabricated device had a low specific on-resistance of 1.1 m/spl Omega/-cm/sup 2/ with a breakdown voltage of -36 V.A novel simplified fabrication method of a very high density p-channel trench gate power MOSFET using four mask layers and nitride/TEOS sidewall spacers is realized. The proposed process showed improved on-resistance characteristics of the device with increasing cell density and the cost-effective production capability due to the lesser number of processing steps. By using this process technique, a remarkably increased high density (100 Mcell/inch/sup 2/) trench gate power MOSFET with a cell pitch of 2.5 /spl mu/m could be effectively realized. The fabricated device had a low specific on-resistance of 1.1 m/spl Omega/-cm/sup 2/ with a breakdown voltage of -36 V.

A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash–SAR Architecture

This brief presents a 10-bit dual-channel pipelined flash-successive approximation register (SAR) analog-to-digital converter (ADC) for high-speed applications. The proposed ADC consists of two channels for high operating speed, and each channel adopts a pipelined flash-SAR architecture for low power and a small area. The proposed flash-SAR ADC in the second stage is composed of a 1-bit flash ADC and a 6-bit SAR ADC considering the chip area, operation speed, and circuit complexity. The prototype ADC fabricated in a 45-nm CMOS process occupies 0.16 mm2. The differential and integral nonlinearities of the ADC are less than 0.36 and 0.67 LSB, respectively. The ADC shows a signal-to-noise-and-distortion ratio of 54.6 dB and a spurious-free dynamic range of 64.0 dB with a 78-MHz input at 230 MS/s with a 1.1-V supply. The maximum operating frequency of the ADC is 260 MS/s at a 1.2-V supply. The power consumptions of the ADC with 230 and 260 MS/s are 13.9 and 17.8 mW, respectively.

A novel technique for fabricating high reliable trench DMOSFETs using self-align technique and hydrogen annealing

A novel technique for fabricating high reliability trench DMOSFETs using three mask layers is realized to obtain cost-effective production capability, higher cell density and current driving capability, and higher reliability. This technique provides a unit cell with 2.3/spl sim/2.4 /spl mu/m pitch and a channel density of 100 Mcell/in/sup 2/. Specific on-resistance is 0.36 m/spl Omega//spl middot/cm/sup 2/ with a blocking voltage of 43 V at a gate voltage of 10 V and 5 A source-to-drain current. The time to breakdown of gate oxide grown on the hydrogen annealed trench surface is much longer than that of oxide grown on a nonhydrogen annealed trench surface.

High-density trench DMOSFETs employing two step trench techniques and trench contact structure

A novel process technique for fabricating trench DMOSFETs using 3 mask layers (trench, poly, metal), two step trench technique, and trench contact structure is realized in order to obtain cost-effective production capability, higher cell density, and better leakage characteristics. A unit cell with a cell pitch of 1.6 /spl mu/m and a channel density of 130Mcell/in/sup 2/ are obtained. The specific on-resistance was 0.28m/spl Omega/-cm/sup 2/ with a blocking voltage of 43 V.

A highly reliable trench DMOSFET employing self-align technique and hydrogen annealing

A novel process technique for fabricating trench double diffused MOSFETs (DMOSFET) using three mask layers is realized in order to obtain cost-effective production capability, higher cell density and current driving capability, and higher reliability. A unit cell with a cell pitch of 2.3/spl sim/2.4 /spl mu/m and a channel density of 100 Mcell/in/sup 2/ are obtained. Specific on-resistance is 0.36 m/spl Omega/.cm/sup 2/ is obtained with a blocking voltage of 43 V. The highly reliable trench DMOSFET was obtained by the formation of the corner rounding of the hydrogen annealed trench surface.

Improvement of breakdown characteristics of LDMOSFETs with uneven racetrack sources for PDP driver applications

The electrical characteristics of n- and p-LDMOSFETs with uneven racetrack source (URS) and conventional racetrack source (CRS) were investigated to apply PDP driver. The breakdown voltage of p-LDMOSFET with URS is 25% higher than that of p-LDMOSFET with CRS and while the saturated drain current of p-LDMOSFET with URS is only 6% lower than that of p-LDMOSFET with CRS. The output of PDP data driver with uneven racetrack LDMOSFETs swings very well from the ground to high supply voltage (130 V) and both rising time and falling time of the output voltage for the PDP data driver were shorter than 160 ns.

Optical characteristics of silicon semiconductor bridges under high current density conditions

The optical emission spectra (180-700 nm) of plasma produced by a semiconductor bridge (SCB) with aluminum or tungsten electrodes have been measured and analyzed. The spatially and temporally resolved emission spectra of the SCB device have provided insights into the dynamic discharge of the bridge. The plasma electron temperature of the SCB device was measured using the comparison of the continuum emission of the bridge with the calculated optical emission spectra for a gray body source. Measured electron temperatures in the plasma produced by the bridges are related to the capacitor discharging voltage. The best estimates indicate that 4100-5500 K was measured for Al-electrode SCB device and 5650-6000 K for W-electrode SCB device.

A novel p-channel SOI LDMOS transistor with tapered field oxides

The on-resistance of p-channel RESURF (reduced surface field) LDMOS (lateral double-diffused MOS) transistors has been improved by using a new tapered TEOS field oxide on the drift region of the devices. With a similar breakdown voltage, at V/sub gs/=-5.0 V, the specific on-resistance of the LDMOS with the tapered field oxide is about 31.5 m/spl Omega//spl middot/cm/sup 2/, while that of the LDMOS with the conventional field oxide is about R/sub sp/=55.3 m/spl Omega//spl middot/cm/sup 2/.

Design of 32 bit Parallel Processor Core for High Energy Efficiency using Instruction-Levels Dynamic Voltage Scaling Technique

This paper describes design of high energy efficiency 32 bit parallel processor core using instruct- tion-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and swit- ching activity of the function units in the proposed data technique. We present instruction-levels DVS tech- nique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage sche- duler controlled by the operation system and a hard- ware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS tech- nique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit pa- rallel processor core can utilize as the coprocessor processing massive data at high speed.