Yi-Gyeong Kim

A ΔΣ ADC using 4-bit SAR type quantizer for audio applications

This paper presents a second-order delta-sigma modulator for audio applications. It uses feed-forward architecture and 4-bit quantizer to enhance linearity and noise performance. A 4-bit successive approximation (SAR) analog-to-digital converter (ADC) with summing operation is implemented to reduce power consumption by eliminating the active summing amplifier. In order to reduce the distortion resulted from the capacitor mismatch of the feedback digital-to-analog converter (DAC), a tree-structured dynamic element matching (DEM) is employed. The prototype delta-sigma ADC implemented in a 45 nm CMOS process occupies 231.2 μm2 and achieves a dynamic range (DR) of 94.0 dB, a peak signal-to-noise ratio (SNR) of 92.1 dB and a peak signal-to-noise and distortion ratio (SNDR) of 84.5 dB for 24 kHz signal bandwidth, while consuming 8.2 mW with 3.3 V supply.

A 105.5 dB, 0.49 mm 2 Audio ΣΔ modulator using chopper stabilization and fully randomized DWA

An audio S.modulator achieves 105.5 dB dynamic range over 20 kHz audio bandwidth. A chopper stabilization technique is used in both the first integrator and the reference buffer to prevent degradation of the dynamic range and the peak signal-to-noise-plus-distortion-ratio due to flicker noise. A fully randomized data weighted averaging is used as a dynamic element matching technique to suppress the generation of spurious tones with a negligible increase in the in-band noise compared to conventional data weighted averaging. The chip was fabricated in 0.13 mum CMOS technology (I/O devices) and occupies a small chip area of 0.49 mm2. The total power consumption is 9.9 mW from a 3.3 V supply.

A 1 V 6-bit 2.4 GS/s Nyquist CMOS DAC for UWB systems

A 6-bit 2.4 GS/s current-steering DAC fabricated in a 65 nm CMOS technology for ultra-wideband (UWB) systems is presented. The prototype achieves a measured spurious-free dynamic range (SFDR) of more than 36 dB over the Nyquist bandwidth at 2.4 GS/s. Among the 50 measured samples, DNL/INL of 0.02/0.02 LSB was the lowest achievable value. The DAC core occupies an area of merely 0.023 mm2 through simplified circuit and careful layout. To operate from a relatively low analog power supply of 1 V, a portion of current cell is implemented using low threshold voltage devices. Total maximum power consumption, including the low voltage differential signaling (LVDS) stage, is 14 mW at 2.4 GS/s.

A 105dB-gain 500MHz-bandwidth 0.1Ω-output-impedance amplifier for an amplitude modulator in 65nm CMOS

Polar modulation, where a constant-amplitude phase signal is amplified by an efficient switched-mode power amplifier (PA) and an envelope signal is modulated at the drain of the PA, has been proven to improve efficiency and linearity of the PA system. However, the amplitude modulator (AM) used in such modulation systems must have wide bandwidth, low switching ripple and high efficiency. Although several AM structures have been reported the hybrid switching amplitude modulator (HSAM) shows excellent performance [1–3]. The HSAM consists of a linear amplifier as a voltage source and a switching amplifier as a dependant current source. The linear amplifier using voltage feedback defines output voltage with high frequency information in a bandwidth-expanded envelope signal and the switching amplifier using current feedback drives almost all the current to develop output voltage with the help of a current sensing circuit. If the current sensing circuit does not work well, it makes an offset to the switching amplifier and results in additional power consumption of the linear amplifier [2]. To meet a stringent spectral mask, low output impedance of the linear amplifier is needed [1]. In conclusion, wide bandwidth and low output impedance of the linear amplifier, and accurate current sensing are critical points in the design of the HSAM.

A CMOS DVD 4/spl times/ speed read channel programmable over 5 octaves

Analog interface functions between optical pick-up and DSP in CD/DVD ROM systems include pulse equalization, one-beam tracking error detection, plus many servo and glue functions such as three-beam tracking error generator for CD, shiny mirror surface detector, defect detector, focus and focus error detectors, envelope detector, laser power control, and reference generators, etc.. To date, pulse equalizer and one-beam tracking error generator have been implemented separately using bipolar, and a digital version has been introduced at the standard DVD speed. This work uses CMOS to integrate all read channel functions up to the DVD 4/spl times/ speed. Technical challenges are 5-octave programmability in the pulse equalizer and delay compensation in the one-beam tracking error detector.