Min Sang Kim

A novel multi-channel field effect transistor (McFET) on bulk Si for high performance sub-80nm application

We demonstrate highly manufacturable double FinFET on bulk Si wafer, named multi-channel field effect transistor (McFET) for the high performance 80nm 144M SRAM. Twin fins are formed for each transistor using our newly developed simple process scheme. McFET with L/sub G/=80nm shows several excellent transistor characteristics, such as /spl sim/5 times higher drive current than planar MOSFET, ideal subthreshold swing of 60mV/dec, drain induced barrier lowering (DIBL) of 15mV/V without pocket implantation, and negligible body bias dependency, maintaining the same source/drain resistance as planar transistor due to the unique feature of McFET.

High-Performance Twin Silicon Nanowire MOSFET (TSNWFET) on Bulk Si Wafer

Gate-all-around twin silicon nanowire MOSFET (TSNWFET) with 5-nm-radius channels on bulk Si wafer is successfully fabricated to achieve extremely high drive currents of 2.37 mA/mum for n-channel and 1.30 mA/mum for p-channel TSNWFETs with mid-gap TiN metal gate. It also shows good short channel effects immunity down to 30 nm gate length due to GAA structure and nanowire channel. The effect of bottom parasitic transistor in TSNWFET is also investigated.

A partially insulated field-effect transistor (PiFET) as a candidate for scaled transistors

Highly manufacturable partially insulated field-effect transistors (PiFETs) were fabricated by using Si-SiGe epitaxial growth and selective SiGe etch process. Owing to these technologies, pseudo-silicon-on-insulator (SOI) structures, partially insulating oxide (PiOX) under source/drain (PUSD) and PiOX under channel (PUC), could be easily realized with excellent structural and process advantages. We are demonstrating their preliminary characteristics and properties. Especially, in the PUSD PiFET, junction capacitance, leakage current, and DIBL in bulk devices could be reduced and the floating body problem in SOI devices was also cleared without any area penalty. Thus, this PiFET structure can be a promising candidate for the future DRAM cell transistor.

Damascene gate FinFET SONOS memory implemented on bulk silicon wafer

We successfully demonstrate highly scaled damascene gate FinFET SONOS memory implemented on bulk silicon wafer. The FinFET SONOS devices show extremely high program/erase speed, large threshold voltage shifts over 4V at 1/spl mu/s/12V for program and 50/spl mu/s/-12V for erase, good retention time, and acceptable endurance. Thus, in sub-50nm regimes, ultra high speed operation becomes possible by using FinFET SONOS structure without sacrificing retention time.

122 Mb High Speed SRAM Cell with 25 nm Gate Length Multi-Bridge-Channel MOSFET (MBCFET) on Bulk Si Substrate

As a part of continued multi-bridge-channel MOSFET (MBCFET) study, we have successfully fabricated 122Mb SRAM cell with 25 nm gate length CMOS MBCFET on bulk Si wafers. The 6-T MBCFET SRAM cell shows high static noise margin (SNM) of 320 mV at Vcc= 0.8 V. Using tall-embedded-gate (TEG) and source/drain (S/D) engineering, 2.6times105 times on/off current ratio and 3.46 mA/mum of on-state current at 13 nA/um of off-state current were achieved. In addition, triple-bridge-channel MOSFET (TBCFET) is made for the first time and compared with single-bridge-channel MOSFET (SBCFET) and MBCFET

Fully working high performance multi-channel field effect transistor (McFET) SRAM cell on bulk Si substrate using TiN single metal gate

We demonstrate for the first time high performance titanium nitride (TiN) single metal gate 65nm CMOS McFET (multichannel field effect transistor) SRAM cell transistor on bulk Si wafer. This single metal gate McFET shows suitable threshold voltage (VT) and excellent transistor characteristics of SS (sub-threshold swing) and DIBL (drain induced barrier lowering) with V/sub TN/ =+0.3V and V/sub TP/=-0.3V. The SRAM cell with this CMOS McFET, high static noise margin (SNM) of 350mV is achieved at 1.0V.

Lateral integration of partially insulated and bulk MOSFETs using partial SOI process

We proposed and successfully demonstrated partially insulated and bulk MOSFETs with multiple V/sub th/s, I/sub on/s, and I/sub Off/s by using partial SOI process without complex process and SOI wafer. Both nMOS and pMOS applicable to the HP and LSTP transistors were simultaneously implemented on the same wafer with the same process except partial SOI process. These results must be very useful to implement IC systems requiring various specifications of V/sub TH/s, I/sub On/s, and I/sub Off/s.

Electrical characterization of partially insulated MOSFETs with buried insulators under source/drain regions

In this article, we evaluated the structural merits of a partially insulated MOSFET (PiFET), for ultimate scaling of planar MOSFETs, through simulation and fabrication. The newly fabricated PiFET showed outstanding short channel effect (SCE) immunity and off-current characteristics over the conventional MOSFET, resulting from a self-induced halo region, self-limiting S/D shallow junction, and reduced junction area due to PiOX layer formation. Thus, the PiFET can be an attractive alternative for ultimate scaling of planar MOSFETs.

High performance twin silicon nanowire MOSFET(TSNWFET) on bulk si wafer

A gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 5-nm-radius channels on a bulk Si wafer is successfully fabricated to achieve extremely high-drive currents of 2.37 mA/ mum for n-channel and 1.30 mA/ mum for p-channel TSNWFETs with mid-gap TiN metal gate that are normalized by a nanowire diameter. It also shows good short-channel effects immunity down to 30-nm gate length due to the GAA structure and the nanowire channel. The effect of bottom parasitic transistor in TSNWFET is also investigated.

Characteristics of MBCFET (Multi-Bridge-Channel MOSFET) with Tall-Embedded-Gate (TEG)

We demonstrate multi-bridge-channel MOSFET (MBCFET) with new gate structure on bulk Si wafer. Sub 25nm MBCFET shows excellent transistor characteristics, such as 750,000 times on/off current ratio and 3.61mA/mum drive current at 4.8nA/mum of off-state current by using tall-embedded-gate (TEG) structure. And thanks to suitable threshold voltage for n,pMBCFET and high current drivability, we successfully achieved high static noise margin (SNM) of 386mA at Vcccc = 1V