Eun-Jung Yoon

High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process. With 10nm diameter nanowire, saturation currents through twin nanowires of 2.64 mA/mum, 1.11 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively. No roll-off of threshold voltages, ~70 mV/dec. of substhreshold swing (SS), and ~20 mV/V of drain induced barrier lowering(DIBL) down to 30 nm gate length are observed for both n-ch and p-ch TSNWFETs

80 nm 512M DRAM with enhanced data retention time using partially-insulated cell array transistor (PiCAT)

An 80 nm 512M DDR DRAM with partially-insulated cell array transistor (PiCAT) was fabricated. Si/SiGe epitaxial growth and selective SiGe etch process were used to form PiOX (Partially-Insulating OXide) under source and drain of the cell transistor. Using these technologies, partial-SOI (Silicon-On-Insulator) structure could be realized with excellent structural and electrical advantages on bulk Si wafer. Self-limited shallow junction under source/drain and halo doping effect at the channel region were formed by PiOX. With PiCAT, junction leakage current and SCE (Short Channel Effect) were reduced, and excellent data retention time was obtained.

Damascene gate FinFET SONOS memory implemented on bulk silicon wafer

We successfully demonstrate highly scaled damascene gate FinFET SONOS memory implemented on bulk silicon wafer. The FinFET SONOS devices show extremely high program/erase speed, large threshold voltage shifts over 4V at 1/spl mu/s/12V for program and 50/spl mu/s/-12V for erase, good retention time, and acceptable endurance. Thus, in sub-50nm regimes, ultra high speed operation becomes possible by using FinFET SONOS structure without sacrificing retention time.

A novel multibridge-channel MOSFET (MBCFET): fabrication technologies and characteristics

We have demonstrated a novel three-dimensional multibridge-channel metal-oxide-semiconductor field-effect transistor (MBCFET). This transistor was successfully fabricated using a conventional complementary metal-oxide-semiconductor process. We introduce the fabrication technologies and electrical characteristics of MBCFET in comparison with a conventional planar MOSFET. The MBCFET has more benefits than a conventional MOSFET. It shows 4.6 times larger current drivability than a planar MOSFET. This is due to the vertically stacked multibridge channels. The subthreshold swing of MBCFET is 61 mV/dec, which is almost an ideal value due to the thin body surrounded by gate. Based on a simulation result, we show that the MBCFET will have a large on-off state current ratio at short channel transistors.

Sub 30 nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance application

We have successfully fabricated sub 30nm N+ poly and TiN gate MBCFET (multi-bridge-channel field effect transistor) both on SOI wafers and bulk-Si wafers. Using TiN metal gate and 20nm multi bridge channels, we achieved the drive current of 2.3mA//spl mu/m that is the largest drive current ever reported for pMOSFETs with excellent subthreshold swing of 75mV/dec, and drain induce barrier lowering (DIBL) of 36mV/V. Large I/sub on//I/sub off/ ratio and excellent threshold voltage (V/sub t/) distribution were obtained using TiN metal gate to eliminate channel ion implantation minimizing the mobility degradation and dopant fluctuation.

Sub-25nm single-metal gate CMOS multi-bridge-channel MOSFET (MBCFET) for high performance and low power application

Improving the MBCFET performance further, we have successfully fabricated single-metal-gate high-performance CMOS MBCFET with elevated flat source/drain (EF-S/D) formed by low temperature cyclic selective epitaxial growth (LTC-SEG) of Si. Due to the S/D engineering and LTC-SEG process, we could achieved the symmetric threshold voltage of 0.25V and -0.22V for TiN-gate n-channel MBCFET (nMBCFET) and p-channel MBCFET (pMBCFET), respectively. This single-metal MBCFET simultaneously satisfied the requirements of high-performance (HP) and low operating power (LOP) transistors in ITRS roadmap.

A novel sub-50 nm multi-bridge-channel MOSFET (MBCFET) with extremely high performance

We demonstrate highly manufacturable sub-50 nm MBCFET with the I/sub on/ of 4.26 mA/ /spl mu/m at V/sub DD/ = 1.2V, which is the best performance ever reported. This excellent performance of the MBCFET is resulted from the vertically stacked channels and enhanced mobility. It has been fabricated on bulk Si substrate by using the multiple epitaxial growth of SiGe/Si/SiGe/Si layers and damascene gate process. It has structural and electrical merits in scaling and process integration.

122 Mb High Speed SRAM Cell with 25 nm Gate Length Multi-Bridge-Channel MOSFET (MBCFET) on Bulk Si Substrate

As a part of continued multi-bridge-channel MOSFET (MBCFET) study, we have successfully fabricated 122Mb SRAM cell with 25 nm gate length CMOS MBCFET on bulk Si wafers. The 6-T MBCFET SRAM cell shows high static noise margin (SNM) of 320 mV at Vcc= 0.8 V. Using tall-embedded-gate (TEG) and source/drain (S/D) engineering, 2.6times105 times on/off current ratio and 3.46 mA/mum of on-state current at 13 nA/um of off-state current were achieved. In addition, triple-bridge-channel MOSFET (TBCFET) is made for the first time and compared with single-bridge-channel MOSFET (SBCFET) and MBCFET

PMOS body-tied FinFET (Omega MOSFET) characteristics

In this paper, we introduce PMOS body-tied FinFet characteristics. For this work, the 0.1/spl mu/m design ruled SRAM technology was used. I/sub D/-V/sub DS/ characteristics show that /spl Omega/ MOSFET apparently has lower DIBL characteristics than conventional PMOS transistor. On current of the /spl Omega/ MOSFET is higher than that of conventional device and can be improved by optimising unit processes.

Fin width scaling criteria of body-tied FinFET in sub-50 nm regime

For better subthreshold swing (SS) and drain induced barrier lowering (DIBL) of FinFETs, the fin width is a more important parameter than the physical gate length. And it should be very thin and fully depleted. In this article, we introduce the fabrication of body-tied FinFETs with various fin widths, fabricated on bulk Si instead of SOI wafer, and propose a new gate length/fin width (L/sub g//W/sub fin/) criterion to get nearly ideal SS and DIBL for body-tied FinFETs. From experiments and simulations, it is proven that threshold voltage (V/sub th/) control is possible even under a 20 nm narrow fin width, and high performance FinFET operation is obtainable even under a 5 nm fin width.