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Dive into the research topics where Yasuhiko Hakotani is active.

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Featured researches published by Yasuhiko Hakotani.


japan international electronic manufacturing technology symposium | 1993

A Stud-bump-bonding Technique For High Density Multi-chip-module

Yoshihiro Bessho; Yoshihiro Tomura; Yasuhiko Hakotani; Masahide Tsukamoto; T. Ishlda; Kazunori Omoya

technique for high density Multi-Chip-Module (MCM), using called Stud-Bump-Bonding (SBB) technique, which can bond bare LSI chips directly to ceramic substrate. Au bump is formed on electrode pad of LSI chip by a wirebonding apparatus. Each Au bump has two-stepped construction and bonded with a conductive adhesive to an electrode terminal formed on the ceramic substrate. The conductive adhesive is very flexible and strong in bond, thus resisting thermal and mechanical stresses. Moreover, repair technique has been developed. 100 ,u m pitch electrode pads of LSI chip can be bonded to electrode terminals. The bonding resistance is less than 50 m i l . memory module. High density and reliability in bonding for MCM have been attained by the SBB technique. We have developed advanced flip-chip bonding We have applied the SBB technique to high density MCM for


japan international electronic manufacturing technology symposium | 1993

Development Of Zero X-y Shrinkage Sintered Ceramic Substrate

Hidenobu Nishikawa; Manabu Tasaki; Seiichi Nakatani; Yasuhiko Hakotani; Minehiro Itagaki

Studies of multilayered ceramic substrate are made briskly ,which makes it possible to design wiring patterns high densely and to mount bare IC chips. The multilayered cbramic substrate is expected for effectiveness for high functional, downsizing and confidential devices. In order to realize high density ceramic Multi-Chip-Module (MCM), multilayered ceramic substrate is required to satisfy demands for fine patterning, small packaging and low cost, Especially, sintering shrinkage of a substrate should be. controlled for fine patteming. Generally, the ceramic substrate undergoes its shrinkage of 10 to 15% and the shrinkage error is *OS%, so the substrate is not suitable for mounting bare IC chips. On considering of such problem, zero X-Y shrinkage sintered ceramic substrate (ZSS) has been developed by the conventional green sheet method, which arranges substrate green sheets between two no-shrinkage sheets, horizontal shrinkage during sintering is prevented to 0.18, and the shrinkage error i s f 0.05%. In this paper, we will report a material, process for prohibiting the horizontal shrinkage and properties of ZSS. .


Archive | 1994

Chip package, a chip carrier, a terminal electrode for a circuit substrate and a chip package-mounted complex

Yoshihiro Tomura; Yoshihiro Bessho; Yasuhiko Hakotani


Archive | 1993

Method for producing multilayered ceramic substrate

Yasuhiko Hakotani; Seiichi Nakatani; Tsuneharu Katada; Satoru Yuhaku; Kazuhiro Miura; Yoshifumi Nakamura


Archive | 1994

Method of manufacturing a ceramic substrate

Yoshifumi Nakamura; Yoshihiro Bessho; Satoru Yuhaku; Yasuhiko Hakotani; Minehiro Itagaki; Kazuhiro Miura


Archive | 1995

Ceramic substrate and manufacturing method thereof

Yoshifumi Nakamura; Yoshihiro Bessho; Satoru Yuhaku; Yasuhiko Hakotani; Minehiro Itagaki; Kazuhiro Miura


Archive | 1990

Dielectric ceramic composition and a multilayer ceramic capacitor and a method of manufacturing a multilayer ceramic capacitor

Yasuhiko Hakotani; Seiichi Nakatani; Satoru Yuuhaku; Tsutomu Nishimura; Toru Ishida


Archive | 1994

Assembly formed from conductive paste and insulating paste

Minehiro Itagaki; Kazuyuki Okano; Suzushi Kimura; Seiichi Nakatani; Yoshihiro Bessho; Satoru Yuhaku; Yasuhiko Hakotani; Kazuhiro Miura


Archive | 1994

Thixotropic conductive paste

Minehiro Itagaki; Yoshihiro Bessho; Satoru Yuhaku; Yasuhiko Hakotani; Kazuhiro Miura; Kazuyuki Okano


Archive | 1995

Methods for producing a chip carrier and terminal electrode for a circuit substrate

Yoshihiro Tomura; Yoshihiro Bessho; Yasuhiko Hakotani

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