Ming-Jer Kao

Reduction in critical current density for spin torque transfer switching with composite free layer

A composite free layer (CFL) consisting of a soft layer and a hard layer exchange coupled in parallel is proposed. The experimental results showed that the critical current density (Jc) can be reduced from 7.05×106A∕cm2 of strong coupled CoFeB(12.5A)∕Ru(4A)∕NiFe(17.5A) CFL to 2.65×106A∕cm2 of weak coupled CoFeB(12.5A)∕Ru(15A)∕NiFe(17.5A) CFL. The macrospin simulations showed that the soft layer of CFL can assist the hard layer of CFL to switch at a lower Jc. These results suggest that by using CFL, it is possible to reduce the Jc of spin torque transfer switching without compromising the thermal stability.

Testing MRAM for Write Disturbance Fault

The magnetic random access memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for read/write operations. It can also endure almost unlimited read/write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC. In this paper, we present the write disturbance fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the write operation. The proposed WDF model is justified by chip measurement results. We also construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results. An MRAM chip has been designed and fabricated using a CMOS-based 0.18mum technology. We also present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. The test is shown to be better and more robust as compared with March C. Finally, we present a March 17N diagnosis algorithm for identifying the WDF

MRAM defect analysis and fault modeling

With the advent of system-on-chip (SOC), the demand for embedded memory cores increases rapidly. The magnetic random access memory (MRAM) is considered one of the potential candidates that replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM has a high speed and does not need high supply voltage for read/write operations, so it has the advantages of RAM and flash memory, making it a potentially good choice for SOC. The testing of MRAM, however, has not been fully investigated. In this work we classify and analyze the MRAM defects and their behavior, and propose its fault models. We have built a SPICE model of MRAM cell and performed defect injection and simulation of a real MRAM circuit. The circuit has been implemented and fabricated with a novel 0.18 m technology. The simulation results regarding the correlation between the defects and conventional fault models show that most of the defects can be covered by the stuck-at fault model. The test data based on the fabricated chips show that the stuck-at faults do cover most of the defects on the chips. However, from the experiment we also have identified two new faults, i.e., the Multi-Victims fault and Kink fault.

Write Disturbance Modeling and Testing for MRAM

The magnetic random access memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for read/write operations, and is compatible with the CMOS technology. It can also endure almost unlimited read/write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC. In this paper, we present the write disturbance fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the write operation. We also construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results. We then present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. The test is shown to be better and more robust as compared with the conventional March C-test algorithm. We also present a March 17 N diagnosis algorithm for identifying WDF. A 1 Mb MRAM chip has been designed and fabricated using a CMOS-based 0.18-mum technology. The proposed WDF model is justified by chip measurement results, with the march test results reported. Finally, specific MRAM fault behavior and test issues are discussed.

Wide operation margin of toggle mode switching for magnetic random access memory with preceding negative pulse writing scheme

In this work, a writing scheme with preceding negative pulse wave form for toggle magnetic random access memory (MRAM) is proposed to enhance the switching yield and enable a low current switching. The failure mechanism of toggle switching is studied by micromagnetic analysis. As a result of broadened operation window and reduced switching current, the scalability of MRAM is feasible with the robust toggle operation.

A 6-F/sup 2/ bit cell design based on one transistor and two uneven magnetic tunnel junctions structure and low power design for MRAM

Novel cell structures based on one transistor and two uneven magnetic tunnel junction cell and pillar write word line architecture are proposed to shrink the bit size with a potential down to 6 F2 by a so-called extended via process, and to reduce the writing current by a factor of 2, combined with the nature of nonvolatility and high speed, making the magnetoresistive random access memory suitable for universal memory applications

Diagnosis of MRAM Write Disturbance Fault

To help improve quality and yield of magnetic random access memory (MRAM), we propose an adaptive diagnosis algorithm (ADA) that can efficiently identify the write disturbance fault (WDF) for MRAM. The proposed test algorithm is a March-based one, i.e., it has linear time complexity and can easily be implemented with built-in self-test (BIST). However, the proposed test method can evaluate the process stability and uniformity using logical test method. We also develop a BIST circuit that supports the proposed WDF diagnosis test method. We propose the BIST scheme based on the decision write mechanism of the toggle MRAM to reduce total test time. A 1 Mb toggle MRAM prototype chip with the proposed BIST circuit has been designed and fabricated using a special 0.15 mum CMOS technology. The BIST circuit overhead is only about 0.04% with respect to the 1 Mb MRAM. The test time is reduced by about 30% as compared with the test method without using the decision write mechanism.

Diagnosis for MRAM write disturbance fault

In this paper, we propose a new test method to detect write disturbance fault (WDF) for magnetic RAM (MRAM). Furthermore, an adaptive diagnosis algorithm (ADA) is also introduced to identify and diagnose the WDF for MRAM. The proposed test method can evaluate process stability and uniformity. We also develop a built-in self-test (BIST) circuit that supports the proposed WDF diagnosis test method. A 1-Mb toggle MRAM prototype chip with the proposed BIST circuit has been designed and fabricated using a special 0.15-μm CMOS technology. The BIST circuit overhead is only about 0.05% with respect to the 1-Mb MRAM. The test time is reduced by about 30% as compared with the test method without using the decision write mechanism. The chip measurement results show the efficiency of our proposed method.

Improvement switching characteristics of toggle magnetic random access memory with dual polarity write pulse scheme

The writing probability of toggle magnetic random access memory (MRAM) at built-in bias field is studied by micromagnetic simulation and a dual polarity write pulse scheme has been proposed to enhance the toggle probability at low writing field. The critical writing field can be reduced to 19Oe at strong built-in bias field from CoFe(1.0nm)∕CoFeB(2.0nm)∕Ru∕CoFe(5.0nm) pinned layer structure. From the simulation and experimental results, it is proven that the toggle MRAM can be operated at lower writing field by dual polarity write pulse scheme.