Young-Shying Chen

Modeling of hot-carrier-stressed characteristics of nMOSFETs

Abstract This paper presents a new degraded drain current model for n MOSFETs with hot-carrier-induced interface states. The model was developed by starting from a two-dimensional Poissons equation and including the effects of series resistances, carrier velocity saturation, and hot-carrier-induced interface states. The nonuniform spatial distribution of interface states is also accounted for in the model. The fitting results show good agreement between the model and the experimental data. The model provides a physics-based approach for modeling forward and reverse MOSFET characteristics with hot-carrier-induced damage and can be easily applied to simulation of device behavior after hot-carrier stress for assessment and improvement of long-term device or circuit reliability.

Testing MRAM for Write Disturbance Fault

The magnetic random access memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for read/write operations. It can also endure almost unlimited read/write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC. In this paper, we present the write disturbance fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the write operation. The proposed WDF model is justified by chip measurement results. We also construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results. An MRAM chip has been designed and fabricated using a CMOS-based 0.18mum technology. We also present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. The test is shown to be better and more robust as compared with March C. Finally, we present a March 17N diagnosis algorithm for identifying the WDF

Modeling of hot-carrier stressed characteristics of submicrometer pMOSFETs

Abstract In a p MOSFET, trapped electrons in the gate oxide due to hot-carrier stress reduce the effective channel length by inverting the surface from an n -type surface to a p -type surface and extend the p drain region. To describe the channel shortening, this paper presents a new analytical, physics-based I - V model for hot-electron damaged submicrometer p -type MOSFETs. The model was developed based on a pseudo-two-dimensional approach, it incorporates the effect of the spatial distribution of trapped electrons and can be used to calculate the degraded channel electric field and potential distribution. The model can also describe the time-dependence of degraded drain current with stress time.

Impact of dislocations and dangling bond defects on the electrical performance of crystalline silicon thin films

A wide variety of liquid and solid phase crystallized silicon films are investigated in order to determine the performance limiting defect types in crystalline silicon thin-film solar cells. Complementary characterization methods, such as electron spin resonance, photoluminescence, and electron microscopy, yield the densities of dangling bond defects and dislocations which are correlated with the electronic material quality in terms of solar cell open circuit voltage. The results indicate that the strongly differing performance of small-grained solid and large-grain liquid phase crystallized silicon can be explained by intra-grain defects like dislocations rather than grain boundary dangling bonds. A numerical model is developed containing both defect types, dislocations and dangling bonds, describing the experimental results.

Write Disturbance Modeling and Testing for MRAM

The magnetic random access memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for read/write operations, and is compatible with the CMOS technology. It can also endure almost unlimited read/write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC. In this paper, we present the write disturbance fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the write operation. We also construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results. We then present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. The test is shown to be better and more robust as compared with the conventional March C-test algorithm. We also present a March 17 N diagnosis algorithm for identifying WDF. A 1 Mb MRAM chip has been designed and fabricated using a CMOS-based 0.18-mum technology. The proposed WDF model is justified by chip measurement results, with the march test results reported. Finally, specific MRAM fault behavior and test issues are discussed.

Wide operation margin of toggle mode switching for magnetic random access memory with preceding negative pulse writing scheme

In this work, a writing scheme with preceding negative pulse wave form for toggle magnetic random access memory (MRAM) is proposed to enhance the switching yield and enable a low current switching. The failure mechanism of toggle switching is studied by micromagnetic analysis. As a result of broadened operation window and reduced switching current, the scalability of MRAM is feasible with the robust toggle operation.

Demonstration of Lateral IGBTs in 4H-SiC

Lateral insulated gate bipolar transistors (IGBTs) in 4H-SiC are demonstrated for the first time. The devices were fabricated based on three different designs to investigate the effects of buffer doping and carrier lifetime on device performance. Experimental results show that, with a lightly doped buffer, a short drift region length, and an improved carrier lifetime, the common base current gain of the parasitic bipolar junction transistor (BJT) is improved, leading to a higher current capability of the IGBT. The differential on-resistance of the lateral IGBT with Ld = 20 μm is smaller than that of a lateral MOSFET counterpart, implying partial conductivity modulation in the drift region.

Modeling and design of the high performance step SOI-LIGBT power devices by partition mid-point method

Abstract In this paper, a partition method is proposed to study the high voltage devices with the step doping profile for the first time. It has been proposed that its breakdown voltage can be approached to that of the linearly graded devices with similar forward voltage drop (Vce). In addition, by this method, the breakdown voltage can be deduced and its corresponding issue location is also fingered out in the step drift region. Furthermore, in order to reduce the undesirable additional masks, the degraded factor (D) is developed to obtain better performance with the least number of frames. Eventually, a 660 V step analytical results are compared with a 606.6 V MEDICI simulation and this shows that the partition method is very effective.

A 6-F/sup 2/ bit cell design based on one transistor and two uneven magnetic tunnel junctions structure and low power design for MRAM

Novel cell structures based on one transistor and two uneven magnetic tunnel junction cell and pillar write word line architecture are proposed to shrink the bit size with a potential down to 6 F2 by a so-called extended via process, and to reduce the writing current by a factor of 2, combined with the nature of nonvolatility and high speed, making the magnetoresistive random access memory suitable for universal memory applications

The switching behaviors of submicron magnetic tunnel junctions with synthetic antiferromagnetic free layers

The switching behaviors in elliptic shaped (aspect ratio=2) submicron magnetic tunnel junctions using CoFeB single free layer and CoFeB∕Ru∕CoFeB synthetic antiferromagnetic (SAF) free layers are studied. It is found that under considerable stray fields originating from pinned layers, junctions with single free layer show complex switching behaviors with larger Hc variations. In contrast, junctions with SAF free layers exhibit kink-free R‐H loops and less Hc variations. The Hc of junctions with SAF free layers is less dependent on the junction size than that with a single free layer. Furthermore, for junctions smaller than a critical size the SAF free layers have a smaller Hc than single free layers.