Ming Ta Hsieh

Architectures for multi-gigabit wire-linked clock and data recovery

Clock and data recovery (CDR) architectures used in high-speed wire-linked communication receivers are often shown as PLL or DLL based topologies. However, there are many other types of CDR architectures such as phase-interpolator, oversampling and injection locked based topologies. The best choice for the CDR topology will depend on the application and the specification requirements. This paper presents an overview and comparative study of the most commonly used CDR architectures. This analysis includes the circuit structures, design challenges, major performance limitations and primary applications. Finally, the tradeoffs among the various CDR architectures are summarized.

Clock and data recovery with adaptive loop gain for spread spectrum SerDes applications

A novel clock and data recovery architecture with adaptive loop gain is proposed for spread spectrum SerDes (serializer/deserializer) applications such as serial AT attachment. The proposed design consists of a half-rate Alexander phase detector, a phase-shifting phase interpolator with a frequency differentiator and an adaptive loop gain filter. The frequency differentiator determines the clock rate difference between the referenced clock and the recovered clock. This value is then used to adjust the gain of the adaptive loop filter for better acquisition of lock with minimized jitter. The proposed design can be implemented in a digital CMOS process which reduces the design difficulty and cost. System operation has been verified using the Cadence SpectreRF and Verilog-A simulators. The results show that the system is capable of recovering /spl plusmn/5000 ppm spread spectrum data with up to a maximum of 0.5 UI of deterministic jitter.

A 900 MHz front-end design with copper passive components

In this paper, we evaluate the impact of copper (Cu) passive components on RF circuit performance. A fully-differential RF Front-end is used as a test vehicle to compare the Cu 0.18 /spl mu/ copper process with a traditional 0.25 /spl mu/ aluminium (Al) process. The RF Front-end contains a balun and a low noise amplifier (LNA) that are designed with spiral inductors and capacitors. CMOS spiral inductor Q values range from 3 to 5 for the aluminium process and are improved with 7 to 9 for the Cu process, while the fringe capacitor Q values for the Cu process are more than twice the Q values for the Al process. At the system level, the balun performance is characterized by its insertion loss and the LNA performance is defined by its gain and noise figure. The balun insertion losses are 0.6 dB to 0.8 dB lower for the Cu process as compared to a traditional Al process. The LNA gain is 3 dB higher for the Cu process and has a sharper bandpass characteristic. The output signals from the LNA are downconverted by a Gibert cell mixer and amplified by an IF stage. The entire system has been simulated and results from measurements are included to validate our simulation result.

Simultaneous bidirectional signaling with adaptive pre-emphasis

This paper presents a novel design for a simultaneous bidirectional signaling system with an adaptive pre-emphasis feature. The feedback loop inherent in a simultaneous bidirectional link provides a natural opportunity to use adaptive pre-emphasis to compensate for channel characteristics. The system determines the degree of corruption of a received signal and generates a pulse width modulated signal which gets sent back through the bidirectional link to control the amount of pre-emphasis that is used. The technique has been verified using Cadence SpectreRF and Verilog-A simulators, where the channel loss characteristics are based on an FR-4 material model. The simulation results show that the system automatically selects the best fit for the observed channel loss compensation, which then reduces the efforts needed to recover the data at each receiver.

A European ISM band power amplifier module

In this paper we present a power amplifier module suitable for the 433 MHz European ISM band frequency. The PA module provides a maximum 30 dBm output level at 433 kHz. The included power control circuit provides 30 dB of dynamic range control. The overall module was designed on a single test board with a 4.8 V supply voltage. The maximum output power deviation is less than 1 dB over the complete control range. Measurements for two tone tests (with a 100 kHz offset) show that the measured intermodulation products are -35 dBc for a -35 dBm input power level. Four different variations of our basic design have been implemented. They differ in the types of directional coupler used and the types of power control circuit used. All designs use directional couplers with an envelope detector for the power control feedback circuit, which offers accurate power detection, high linearity and stable output power. The inherent simplicity of the new design makes it useful for many applications. At the highest output power level, the measured power efficiency of the PA module is 40%.

Simultaneous bidirectional PAM-6 wired link with adaptive pre-emphasis and trellis coding

This work presents a novel design for a simultaneous bidirectional multilevel wireline transmission system with adaptive pre-emphasis and trellis coded modulation. The incorporation of a trellis encoder and a Viterbi decoder provides coding gain to offset the loss of SNR caused by the multilevel pulse amplitude modulation. Furthermore, the feedback loop inherent in a simultaneous bidirectional link provides a natural opportunity to use adaptive pre-emphasis to compensate for channel characteristics. Our simulation results demonstrate the effectiveness of this approach.

Modeling and verification of high-speed wired links with Verilog-AMS

Behavioral modeling with virtual built-in self-test verification of high-speed wired link designs is described in this paper. Our procedure is based on principles of top-down mixed-signal design combined with a behavioral description language and mixed-mode simulations. The use of Verilog-AMS is applied not only to circuit modeling but also for representing noise on the input signal. This approach provides system-level jitter tolerance estimation, circuit critical path search and overall design verification. Coding examples and simulation results are included

Power optimization of CMOS LC VCOs

A technique is presented for the minimization of power consumption in a LC tank voltage-controlled oscillator for low-power wireless systems, such as wireless sensors. This technique involves finding the power constraints for a given inductor design, and then making an optimal tradeoff between inductor series resistance and stray capacitance. The technique and the analytic model are then used to optimize the power consumption of an LC oscillator. The oscillator performance is verified via simulation. The simulated performance matches the predicted performance well. Optimized designs using this technique can result in 100% or more reduction of power in comparison to sub-optimal design.

Simultaneous bidirectional PAM-4 link with built-in self-test

This paper presents a new design of a simultaneous bidirectional PAM-4 wired transmission system that uses built-in self-test (BIST) to adjust the level of pre-emphasis that is applied. The BIST circuitry consists of a pattern generator and detector, a signal comparator and a high-pass filter. It outputs an error indicator that is used as a control signal in the adaptive pre-emphasis block. The feedback loop inherent in a simultaneous bidirectional link provides a natural opportunity to carry information about the channel characteristics without the need for an extra dedicated wire. The design has been verified using the Cadence SpectreRF and Verilog-A simulators and the channel loss characteristics are based on an FR-4 material model extracted from the Cadence Transmission Line Model Generator.