Miquel L. Alomar

A New Stochastic Computing Methodology for Efficient Neural Network Implementation

This paper presents a new methodology for the hardware implementation of neural networks (NNs) based on probabilistic laws. The proposed encoding scheme circumvents the limitations of classical stochastic computing (based on unipolar or bipolar encoding) extending the representation range to any real number using the ratio of two bipolar-encoded pulsed signals. Furthermore, the novel approach presents practically a total noise-immunity capability due to its specific codification. We introduce different designs for building the fundamental blocks needed to implement NNs. The validity of the present approach is demonstrated through a regression and a pattern recognition task. The low cost of the methodology in terms of hardware, along with its capacity to implement complex mathematical functions (such as the hyperbolic tangent), allows its use for building highly reliable systems and parallel computing.

FPGA-based stochastic echo state networks for time-series forecasting

Hardware implementation of artificial neural networks (ANNs) allows exploiting the inherent parallelism of these systems. Nevertheless, they require a large amount of resources in terms of area and power dissipation. Recently, Reservoir Computing (RC) has arisen as a strategic technique to design recurrent neural networks (RNNs) with simple learning capabilities. In this work, we show a new approach to implement RC systems with digital gates. The proposed method is based on the use of probabilistic computing concepts to reduce the hardware required to implement different arithmetic operations. The result is the development of a highly functional system with low hardware resources. The presented methodology is applied to chaotic time-series forecasting.

High-Density Liquid-State Machine Circuitry for Time-Series Forecasting

Spiking neural networks (SNN) are the last neural network generation that try to mimic the real behavior of biological neurons. Although most research in this area is done through software applications, it is in hardware implementations in which the intrinsic parallelism of these computing systems are more efficiently exploited. Liquid state machines (LSM) have arisen as a strategic technique to implement recurrent designs of SNN with a simple learning methodology. In this work, we show a new low-cost methodology to implement high-density LSM by using Boolean gates. The proposed method is based on the use of probabilistic computing concepts to reduce hardware requirements, thus considerably increasing the neuron count per chip. The result is a highly functional system that is applied to high-speed time series forecasting.

Ultra-Fast Data-Mining Hardware Architecture Based on Stochastic Computing

Minimal hardware implementations able to cope with the processing of large amounts of data in reasonable times are highly desired in our information-driven society. In this work we review the application of stochastic computing to probabilistic-based pattern-recognition analysis of huge database sets. The proposed technique consists in the hardware implementation of a parallel architecture implementing a similarity search of data with respect to different pre-stored categories. We design pulse-based stochastic-logic blocks to obtain an efficient pattern recognition system. The proposed architecture speeds up the screening process of huge databases by a factor of 7 when compared to a conventional digital implementation using the same hardware area.

A Stochastic Spiking Neural Network for Virtual Screening

Virtual screening (VS) has become a key computational tool in early drug design and screening performance is of high relevance due to the large volume of data that must be processed to identify molecules with the sought activity-related pattern. At the same time, the hardware implementations of spiking neural networks (SNNs) arise as an emerging computing technique that can be applied to parallelize processes that normally present a high cost in terms of computing time and power. Consequently, SNN represents an attractive alternative to perform time-consuming processing tasks, such as VS. In this brief, we present a smart stochastic spiking neural architecture that implements the ultrafast shape recognition (USR) algorithm achieving two order of magnitude of speed improvement with respect to USR software implementations. The neural system is implemented in hardware using field-programmable gate arrays allowing a highly parallelized USR implementation. The results show that, due to the high parallelization of the system, millions of compounds can be checked in reasonable times. From these results, we can state that the proposed architecture arises as a feasible methodology to efficiently enhance time-consuming data-mining processes such as 3-D molecular similarity search.

Digital Implementation of a Single Dynamical Node Reservoir Computer

Minimal hardware implementations of machine-learning techniques have been attracting increasing interest over the last decades. In particular, field-programmable gate array (FPGA) implementations of neural networks (NNs) are among the most appealing ones, given the match between system requirements and FPGA properties, namely, parallelism and adaptation. Here, we present an FPGA implementation of a conceptually simplified version of a recurrent NN based on a single dynamical node subject to delayed feedback. We show that this configuration is capable of successfully performing simple real-time temporal pattern classification and chaotic time-series prediction.

Low-cost hardware implementation of Reservoir Computers

The hardware implementation of massive Recurrent Neural Networks to efficiently perform time dependent signal processing is an active field of research. In this work we review the basic principles of stochastic logic and its application to the hardware implementation of Neural Networks. In particular, we focus on the implementation of the recently introduced Reservoir Computer architecture. We show the functionality and low hardware resources used to implement the Reservoir Computer by synthesizing a network performing a mathematical regression.

Noise-robust hardware implementation of neural networks

Efficient hardware implementations of neural networks are of high interest. Stochastic computing is an alternative to conventional digital logic that allows to exploit the intrinsic parallelism of neural networks using few hardware resources. We present a new stochastic methodology that extends the capabilities of classical stochastic computing. In particular, the present approach exhibits practically total immunity to noise. This is demonstrated evaluating the influence of the noise on the systems performance for a mathematical regression task.

Cyclic Reservoir Computing with FPGA Devices for Efficient Channel Equalization

The reservoir computation (RC) is a recurrent neural network architecture that is very suitable for time series prediction tasks. Its implementation in specific hardware can be very useful in relation to software approaches, especially when low consumption is an essential requirement. However, the hardware realization of RC systems is expensive in terms of circuit area and power dissipation, mainly due to the need of a large number of multipliers at the synapses. In this paper, we present an implementation of an RC network with cyclic topology (simple cyclic reservoir) in which we limit the available synapses’ weights, which makes it possible to replace the multiplications with simple addition operations. This design is evaluated to implement the equalization of a non-linear communication channel, and allows significant savings in terms of hardware resources, presenting an accuracy comparable to previous works.

Stochastic hardware implementation of Liquid State Machines.

The hardware implementation of neural network models allows to efficiently exploit their inherent parallelism. Here, we focus on the Liquid State Machine (LSM) methodology to build recurrent Spiking Neural Networks (SNN), particularly suited to process time-dependent signals. We propose a low cost hardware implementation of LSM networks based on the use of stochastic computing (SC) concepts. The functionality of the present approach is demonstrated for a time-series prediction task.