Vincent Canals

Chaos-based mixed signal implementation of spiking neurons.

A new design of Spiking Neural Networks is proposed and fabricated using a 0.35 microm CMOS technology. The architecture is based on the use of both digital and analog circuitry. The digital circuitry is dedicated to the inter-neuron communication while the analog part implements the internal non-linear behavior associated to spiking neurons. The main advantages of the proposed system are the small area of integration with respect to digital solutions, its implementation using a standard CMOS process only and the reliability of the inter-neuron communication.

Hardware implementation of stochastic spiking neural networks.

Spiking Neural Networks, the last generation of Artificial Neural Networks, are characterized by its bio-inspired nature and by a higher computational capacity with respect to other neural models. In real biological neurons, stochastic processes represent an important mechanism of neural behavior and are responsible of its special arithmetic capabilities. In this work we present a simple hardware implementation of spiking neurons that considers this probabilistic nature. The advantage of the proposed implementation is that it is fully digital and therefore can be massively implemented in Field Programmable Gate Arrays. The high computational capabilities of the proposed model are demonstrated by the study of both feed-forward and recurrent networks that are able to implement high-speed signal filtering and to solve complex systems of linear equations.

A New Stochastic Computing Methodology for Efficient Neural Network Implementation

This paper presents a new methodology for the hardware implementation of neural networks (NNs) based on probabilistic laws. The proposed encoding scheme circumvents the limitations of classical stochastic computing (based on unipolar or bipolar encoding) extending the representation range to any real number using the ratio of two bipolar-encoded pulsed signals. Furthermore, the novel approach presents practically a total noise-immunity capability due to its specific codification. We introduce different designs for building the fundamental blocks needed to implement NNs. The validity of the present approach is demonstrated through a regression and a pattern recognition task. The low cost of the methodology in terms of hardware, along with its capacity to implement complex mathematical functions (such as the hyperbolic tangent), allows its use for building highly reliable systems and parallel computing.

Hardware implementation of stochastic-based Neural Networks

In this work we review the basic principles of stochastic logic and its application to the hardware implementation of Neural Networks. In this paper we show the mathematical basis of stochastic-based neurons along with the specific circuits that are needed to implement the processing of each neuron. We also propose a new methodology to reproduce the non-linear activation function. The proposed methodology can be used to implement any kind of Neural Network

FPGA-based stochastic echo state networks for time-series forecasting

Hardware implementation of artificial neural networks (ANNs) allows exploiting the inherent parallelism of these systems. Nevertheless, they require a large amount of resources in terms of area and power dissipation. Recently, Reservoir Computing (RC) has arisen as a strategic technique to design recurrent neural networks (RNNs) with simple learning capabilities. In this work, we show a new approach to implement RC systems with digital gates. The proposed method is based on the use of probabilistic computing concepts to reduce the hardware required to implement different arithmetic operations. The result is the development of a highly functional system with low hardware resources. The presented methodology is applied to chaotic time-series forecasting.

High-Density Liquid-State Machine Circuitry for Time-Series Forecasting

Spiking neural networks (SNN) are the last neural network generation that try to mimic the real behavior of biological neurons. Although most research in this area is done through software applications, it is in hardware implementations in which the intrinsic parallelism of these computing systems are more efficiently exploited. Liquid state machines (LSM) have arisen as a strategic technique to implement recurrent designs of SNN with a simple learning methodology. In this work, we show a new low-cost methodology to implement high-density LSM by using Boolean gates. The proposed method is based on the use of probabilistic computing concepts to reduce hardware requirements, thus considerably increasing the neuron count per chip. The result is a highly functional system that is applied to high-speed time series forecasting.

Ultra-Fast Data-Mining Hardware Architecture Based on Stochastic Computing

Minimal hardware implementations able to cope with the processing of large amounts of data in reasonable times are highly desired in our information-driven society. In this work we review the application of stochastic computing to probabilistic-based pattern-recognition analysis of huge database sets. The proposed technique consists in the hardware implementation of a parallel architecture implementing a similarity search of data with respect to different pre-stored categories. We design pulse-based stochastic-logic blocks to obtain an efficient pattern recognition system. The proposed architecture speeds up the screening process of huge databases by a factor of 7 when compared to a conventional digital implementation using the same hardware area.

Stochastic-based pattern-recognition analysis

In this work we review the basic principles of stochastic logic and propose its application to probabilistic-based pattern-recognition analysis. The proposed technique is intrinsically a parallel comparison of input data to various pre-stored categories using Bayesian techniques. We design smart pulse-based stochastic-logic blocks to provide an efficient pattern-recognition analysis. The proposed architecture is applied to a specific navigation problem.

Probabilistic-based neural network implementation

This paper addresses a simple way for neural network hardware implementation based on probabilistic methodologies. We propose a new codification scheme that can be considered as an extension of stochastic computing (unipolar and bipolar codification formats), extending its representation range to any real number by using the ratio between two bipolar coded pulsed signals as codification method. Based on this codification, we propose the implementation of different linear and non-linear stochastic computational elements to be employed in artificial neural networks. Also this paper presents the accuracy associated to the proposed processing. The validation of the presented approach has been done with a sample application, (a spatial pattern classification example). The low cost in terms of hardware of the proposed methodology, along with the complexity of the mathematical expressions that can be implemented allows its use for massive parallel computing.

Short-Term Spanish Aggregated Solar Energy Forecast

This work presents and compare six short-term forecasting methods for hourly aggregated solar generation. The methods forecast one day ahead hourly values of Spanish solar generation. Three of the models are based on MLP network and the other three are based on NARX. The two different types of NN use to forecast the same NWP data, comprising solar radiation, solar irradiation and the cloudiness index weighted with the installed solar power for the whole country. In addition of the NWP data the models are fed with the aggregated solar energy generation in hourly step given by the System Operator.