Mireia Bargallo Gonzalez

Stretching-induced interconnect delamination in stretchable electronic circuits

Stretchable electronics offer increased design freedom of electronic products. Typically, small rigid semiconductor islands are interconnected with thin metal conductor lines on top of, or encapsulated in, a highly compliant substrate, such as a rubber material. A key requirement is large stretchability, i.e. the ability to withstand large deformations during usage without any loss of functionality. Stretching-induced delamination is one of the major failure modes that determines the amount of stretchability that can be achieved for a given interconnect design. During peel testing, performed to characterize the interface behaviour, the rubber is severely lifted at the delamination front while at the same time fibrillation of the rubber at the peel front is observed by ESEM analyses. The interface properties are established by combining the results of numerical simulations and peeling experiments at two distinct scales: the global force–displacement curves and local rubber lift geometries. The thus quantified parameters are used to predict the delamination behaviour of zigzag- and horseshoe-patterned interconnect structures. The accuracy of these finite element simulations is assessed by a comparison of the calculated evolution of the shape of the interconnect structures and the fibrillation areas during stretching with experimental results obtained by detailed in situ analyses.

Towards a TILLING platform for functional genomics in Piel de Sapo melons

BackgroundThe availability of genetic and genomic resources for melon has increased significantly, but functional genomics resources are still limited for this crop. TILLING is a powerful reverse genetics approach that can be utilized to generate novel mutations in candidate genes. A TILLING resource is available for cantalupensis melons, but not for inodorus melons, the other main commercial group.ResultsA new ethyl methanesulfonate-mutagenized (EMS) melon population was generated for the first time in an andromonoecious non-climacteric inodorus Piel de Sapo genetic background. Diverse mutant phenotypes in seedlings, vines and fruits were observed, some of which were of possible commercial interest. The population was first screened for mutations in three target genes involved in disease resistance and fruit quality (Cm-PDS, Cm-eIF4E and Cm-eIFI(iso)4E). The same genes were also tilled in the available monoecious and climacteric cantalupensis EMS melon population. The overall mutation density in this first Piel de Sapo TILLING platform was estimated to be 1 mutation/1.5 Mb by screening four additional genes (Cm-ACO1, Cm-NOR, Cm-DET1 and Cm-DHS). Thirty-three point mutations were found for the seven gene targets, six of which were predicted to have an impact on the function of the protein. The genotype/phenotype correlation was demonstrated for a loss-of-function mutation in the Phytoene desaturase gene, which is involved in carotenoid biosynthesis.ConclusionsThe TILLING approach was successful at providing new mutations in the genetic background of Piel de Sapo in most of the analyzed genes, even in genes for which natural variation is extremely low. This new resource will facilitate reverse genetics studies in non-climacteric melons, contributing materially to future genomic and breeding studies.

Simulation of thermal reset transitions in resistive switching memories including quantum effects

An in-depth study of reset processes in RRAMs (Resistive Random Access Memories) based on Ni/HfO2/Si-n+ structures has been performed. To do so, we have developed a physically based simulator where both ohmic and tunneling based conduction regimes are considered along with the thermal description of the devices. The devices under study have been successfully fabricated and measured. The experimental data are correctly reproduced with the simulator for devices with a single conductive filament as well as for devices including several conductive filaments. The contribution of each conduction regime has been explained as well as the operation regimes where these ohmic and tunneling conduction processes dominate.

Elastic and Conformable Electronic Circuits and Assemblies using MID in polymer

For user comfort reasons, electronic circuits for implantation in the human body or for use as smart clothes should ideally be soft, stretchable and elastic. In this contribution the initial results of an MID (moulded interconnect device) technology will be presented, showing the feasibility of functional stretchable electronic circuits. In the developed technology rigid or flexible standard components are interconnected by meander shaped electroplated metallic wires and embedded by molding in a stretchable substrate polymer, like silicone rubber or polyurethane. The meander design was supported by mechanical simulations in order to minimize the stress in the metal during deformation. In this way reliable stretchability of the circuits above 100% has been demonstrated. A simple stretchable thermometer circuit with 4 components embedded in Dow Corning Silasticreg PDMS silicone material has been built and proper operation has been demonstrated.

3D stacking induced mechanical stress effects

In this work the effects of 3D stacking technology on the performance of devices are systematically studied. For this study a special chip consisting of a number of stress sensors and vertical interconnect loops was designed and manufactured in 65 nm technology. Local variations of stress with a magnitude of up to 300 MPa are detected at different locations along the chip and are being characterized using finite element modeling and micro-Raman spectroscopy measurements.

Analysis of microbump induced stress effects in 3D stacked IC technologies

Besides the stress around Cu TSVs, also the stress induced by microbumps is a main contributor to transistor level stress. For complete and successful deployment of 3D IC all effects generating stress have to be addressed. Therefore, this work quantifies the stress and its effects associated with Cu microbumps and their interaction with underfill material in 3D stacks by using a combined experimental and theoretical approach. We report on the stress generated by backside microbumps affecting FETs through the thinned silicon die and the stress on the thin die caused by 3D stacking. We find that the FET current shifts reach over 40% due to the impact of stress. Additionaly, a FEM parametric study was performed to determine key stress reduction contributors in 3D stacks.

Chip package interaction (CPI): Thermo mechanical challenges in 3D technologies

The residual stresses generated during different processing steps and during thermal cycling of 3D stack packages, mimicking its service life, are quantified by Finite Element Modeling (FEM) together with measurements of dedicated FET arrays used as CPI sensors. Thermo-mechanical deformation of the package can be directly transferred to the Cu/low-k interconnect, inducing large local stresses to drive interfacial crack formation and propagation. The test vehicle used in this work is an imecs proprietary logic CMOS IC on top of which a commercial DRAM is stacked. Different test structures contained in the chip, allow monitoring thermo-mechanical stresses and electrical characteristics of TSVs and micro-bumps. It is shown that FET current shifts can be used to measure the stress in the surface of the chip. The use of standard FEM approach is insufficient to simulate the CPI due to the large dimensional difference between the packaging and interconnects structures. Due to size and speed limitations of commercial computers, a 3D thermo mechanical model of a 3D package cannot contain all the details from the package and at the same time simulate the small structures such as metal and dielectric layers in the BEOL. For this reason, multi-scale simulations are the best choice for identifying the critical regions of the package where high stresses and/or delamination failures are expected to occur. We have shown the methodology to follow to study the CPI.

Charge trapping analysis of Al2O3 films deposited by atomic layer deposition using H2O or O3 as oxidant

In this work, the authors focus on the charge trapping behavior of Al2O3 layers deposited by atomic layer deposition. The goal is to give an insight into the effects of the oxidant source (H2O or O3) and the postdeposition anneal on the charging phenomena and the generation of new defects during electrical stress. For this purpose, current–voltage, capacitance–voltage, and conductance–voltage characteristics of Al/Al2O3/p-Si capacitors are analyzed before and after constant voltage stress and several phenomena such as the generation of neutral traps in the bulk dielectric, slow states, interface states, and charge trapping related degradation during the electrical stress are investigated. Finally, the impact of the oxidant source on the Al2O3 layer reliability is discussed.

In-depth study of the physics behind resistive switching in TiN/Ti/HfO2/W structures

A physical simulation procedure was used to describe the processes behind the operation of devices based on TiN/Ti/HfO2/W structures. The equations describing the creation and destruction of conductive filaments formed by oxygen vacancies are solved in addition to the heat equation. The resistances connected with the metal electrodes were also considered. Resistive random access memories analyzed were fabricated, and many of the characteristics of the experimental data were reproduced with accuracy. Truncated-cone shaped filaments were employed in the model developed with metallic-like transport characteristics. A hopping current was also taken into account to describe the electron transport between the filament tip and the electrode. Hopping current is an essential component in the device high resistance state.

Optimal choice of the FEM damage volumes for estimation of the solder joint reliability for electronic package assemblies

The objective of this study is to define a more thorough and systematic method for selecting the damage volume. The damage volume has heeo optimised for a particular type of CSP. Thanks to the availability of test results for about 20 different configurations, the optimal damage volume could he found. It has been depicted that the optimal damage volume is a choice of a few elements selected out of two layers of elements near the location of highest strain. A similar accuracy is achieved when the two top layers of element is selected. However selecting only the top layer of elements overestimates the effect of the solder joint shape, and underestimates the effect of distance to neutral point. A different conclusion has been found for non-underfilled flip chip assemblies. Instead of using a fxed thickness of the damage volume for the CPSs, we have to use a damage volume proportional to the solder joint stand-off height. The reason is that the whole solder joint is deforming, while for the CSP, mainly the two top layers of elements take up the largest deformations. For other packages such as ceramic hall grid arrays (CBGA), quad flat package (e.g. QFN) and the polymer stud grid array (PSGA), an accurate empirical model is found hut it was not possible to find a closed method to defme the optimal damage volume due to the limited number of reliability data.