J. Martin-Martinez

Ubiquitous relaxation in BTI stressing—New evaluation and insights

The ubiquity of threshold voltage relaxation is demonstrated in samples with both conventional and high-k dielectrics following various stress conditions. A technique based on recording short traces of relaxation during each measurement phase of a standard measure-stress-measure sequence allows monitoring and correcting for the otherwise-unknown relaxation component. The properties of relaxation are discussed in detail for pFET with SiON dielectric subjected to NBTI stress. Based on similarities with dielectric relaxation, a physical picture and an equivalent circuit are proposed.

Emerging yield and reliability challenges in nanometer CMOS technologies

With further scaling of nanometer CMOS technologies, yield and reliability become an increasing challenge. This paper reviews the most important phenomena affecting yield and reliability. For each effect, the basic physical mechanisms causing the effect and its impact on transistor parameters are described. Possible solutions to cope/handle with these effects on the design level are discussed as well.

NBTI from the perspective of defect states with widely distributed time scales

Broad similarity between negative bias temperature instability (NBTI) relaxation and 1/ƒ noise is observed. Individual transitions in NBTI relaxation in small pFETs are observed and Poisson defect number statistics is inferred. Finally, it is argued that the wide distribution of defect times should be considered in addition to defect number variation in small devices.

Gate Oxide Wear-Out and Breakdown Effects on the Performance of Analog and Digital Circuits

To investigate the impact of gate oxide degradation and breakdown (BD) on complimentary metal-oxide-semiconductor circuit functionality, an accurate description of the electrical characteristics of the stressed devices, which can be included in circuit simulators, is needed. In this paper, a description of the stressed device performance that considers, on the one hand, the variation of the channel current and, on the other, the increase in the gate current due to the oxide degradation and BD is presented, which is able to account for different levels of oxide damage. The parameters extracted from device experimental data have been introduced in a circuit simulator to evaluate the effect of the oxide degradation and BD on simple analog (current mirror) and digital [reset set (RS) latches] circuits. The impact of the increase in the gate leakage current and the variation of the conduction along the metal-oxide-semiconductor field-effect transistor channel due to the oxide degradation on the circuit performances has been separately analyzed.

Probabilistic defect occupancy model for NBTI

A new Negative Bias Temperature Instability (NBTI) model based on the probability of charge/discharge of defects in devices is presented. The model correctly describes the main experimental NBTI features, such as the threshold voltage shift (ΔVT) evolution under DC or AC stresses, its frequency and duty cycle dependence and the statistical ΔVT distribution in small transistors. Finally, the model is used to explain the dependence of NBTI degradation on the stress/relaxation times, frequency and duty cycle in terms of defect occupancy.

Time-Dependent Variability Related to BTI Effects in MOSFETs: Impact on CMOS Differential Amplifiers

With the continuous transistor scaling, device mismatch related to intrinsic process variability increases and becomes one of the most important problems to be faced during circuit design. In addition, gate oxide wear-out strongly affects the device reliability and adds a time dependence to device mismatch. In this paper, the impact on circuit functionality of both process variability and gate oxide degradation is studied. First, the effect of the gate oxide damage on the NMOS and PMOS transistor characteristics and their variability has been analyzed. Second, a methodology based on combined SPICE and Monte Carlo simulations to analyze the time-dependent variability at device and circuit levels is presented, which has allowed to reproduce the experimental data. Finally, using the proposed methodology, the influence of the process variability and gate oxide wear-out on the functionality of different configurations of an amplifier circuit was investigated. The results show that both aspects can be decisive in the circuit reliability.

Time-dependent variability of high-k based MOS devices: Nanoscale characterization and inclusion in circuit simulators

Integrated circuit performance and/or reliability can be compromised because of the time-dependent variability observed in ultra-scaled devices, which arises from atomic scale process related variations and aging mechanisms acting during circuit operation. Therefore, extensive characterization and modeling of the nanoscale underlying phenomena is needed, so that their effects could be predicted and propagated to upper (device and circuit) levels, as dictated by the Reliability-Aware Design methodology. This paper is focused on the time-dependent shifts coming from the gate dielectric in MOS devices. Different approaches to characterize (at the nanoscale), model (at device level) and simulate (in a circuit) the related phenomena are reviewed.

New Weighted Time Lag Method for the Analysis of Random Telegraph Signals

A new method for the characterization of random telegraph signals (RTSs) is presented. The method, which is based on the time lag plot, is illustrated using Monte Carlo generated RTS traces and applied to identify the contribution of defects in multilevel RTS measured in a pMOS transistor. The results show that the new method provides a powerful and easily implementable technique to obtain the parameters of the defects responsible of multilevel RTS, even when the background noise is relevant.

Reversible dielectric breakdown in ultrathin Hf based high-k stacks under current-limited stresses

The effects of a current-limited breakdown (BD) on the post-BD current of MOS capacitors with a thin high-k dielectric stack have been analysed. A strong current reduction after BD and, consequently, a partial recovery of the insulating properties of the dielectric stack is observed. The similarities with the resistive switching phenomenon observed in MIM structures for memory applications are discussed.

Recovery of the MOSFET and Circuit Functionality After the Dielectric Breakdown of Ultrathin High-

The reversibility of the gate dielectric breakdown (DB) in ultrathin high-k dielectric stacks is reported and analyzed. The electrical performance of MOSFETs after the dielectric recovery is modeled and introduced in a circuit simulator. The simulation of several digital circuits shows that their functionality can be restored after the DB recovery.