M. Nafria

Polycrystallization effects on the nanoscale electrical properties of high-k dielectrics

In this study, atomic force microscopy-related techniques have been used to investigate, at the nanoscale, how the polycrystallization of an Al2O3-based gate stack, after a thermal annealing process, affects the variability of its electrical properties. The impact of an electrical stress on the electrical conduction and the charge trapping of amorphous and polycrystalline Al2O3 layers have been also analyzed.

Nanoscale post-breakdown conduction of HfO/sub 2//SiO/sub 2/ MOS gate stacks studied by enhanced-CAFM

An enhanced conductive atomic force microscope has enabled a measurement of the conduction through a HfO/sub 2//SiO/sub 2/ gate stack until breakdown (BD) in a single measurement, with nanometer resolution. Before the stack BD, the current-voltage characteristic shows several conduction modes. After BD, switchings between different conduction states were observed, showing that BD is a reversible phenomenon.

Nanoscale observations of the electrical conduction of ultrathin SiO/sub 2/ films with conducting atomic force microscopy

A conductive atomic force microscope (C-AFM) has been used to investigate the conduction properties of electrically stressed ultrathin (<6 nm) films of SiO/sub 2/. Working on bare gate oxides, the conductive tip of the C-AFM allows the electrical characterization of nanometric areas. Due to the extremely small size of the analysed area, several features not registered during macroscopic tests are observed. In particular, before the oxide breakdown, switching between different conduction states and sudden changes of conductivity have been measured, which have been related to the pre-breakdown noise observed in conventional MOS structures. Moreover, similar switchings have been also measured after the oxide breakdown, which have been related to the opening or closure of conduction channels between the electrodes. The phenomenology observed with the C-AFM provides experimental evidence of the local nature of the degradation and breakdown phenomena. Therefore, the C-AFM is a powerful tool to analyse the microscopic physics of the degradation and breakdown of ultrathin SiO/sub 2/ films at the same dimensional scale at which they take place.

Relation between degradation and breakdown of thin SiO 2 films under AC stress conditions

Abstract MOS capacitors have been subjected to bipolar voltage waveforms of different amplitudes and frequencies. The current density measured under a DC low-value gate voltage is taken as an indicator of the oxide degradation level, so that its evolution is taken as a measure of the progressive wearout of the oxide. The data suggest lower degradation levels, for the same stress times, at high frequencies. This is consistent with the increase of the time-to-breakdown with frequency and confirms that, also for dynamic stresses, the relation between degradation and breakdown is fundamental to understand the physics of dielectric breakdown.

Imaging breakdown spots in SiO/sub 2/ films and MOS devices with a conductive atomic force microscope

Conductive Atomic Force Microscopy (C-AFM) is used to study the dielectric breakdown of ultrathin SiO/sub 2/ layers at a nanometric scale. First, bare oxide regions have been stressed and broken down using the tip as the metal electrode of a MOS structure. The results point out that the initial breakdown is electrically propagated to neighbour regions, affecting their dielectric strength. Moreover, the area affected by the initial breakdown depends on the breakdown hardness. In particular, it is shown that this area is smaller when the current through the structure is limited during the experiments. The effect of the current limitation is analysed in detail. Based on the results, a qualitative picture of the breakdown process is presented, which accounts for this effect. Finally, for the first time, the BD spots in standard MOS devices (with poly-Si gate) are electrically imaged with the C-AFM. The areas of the observed spots are in agreement with those obtained on bare oxides.

New insights into the wide ID range channel hot-carrier degradation in high-k based devices

At low energy range, the Lucky Electron Model does not describe correctly the Channel Hot-Carrier (CHC) degradation for transistors with both SiO2 and high-k dielectric. A new picture to explain the CHC degradation behavior in nMOSFETs based on the dominant role of the gate voltage into the total CHC stress is presented.

Simulation of BTI-Related Time-Dependent Variability in CMOS Circuits

The correct evaluation of BTI impact on the circuit performance and reliability is a major concern in current technologies. Since BTI in ultrascaled devices is a stochastic mechanism and aging must be evaluated under the actual operation conditions of devices in the circuit, SPICE and Monte Carlo simulations are customary combined with this purpose. The key point in these simulations is the correct description of the BTI effects in the device and their inclusion in circuit simulators. In this subchapter, the different adopted approaches are presented, pointing out their pros and cons, and illustrated with examples of BTI effects on several analog and digital circuits.

Experimental verification of memristor-based material implication NAND operation

Memristors are being considered as promising devices for highly dense memory systems as well as the potential basis of new computational paradigms. In this scenario, and in relation with data processing, one of the more specific and differential logic functions is the material implication logic also named as IMPLY logic. Many papers have been published in this framework but few of them are related with experimental works using real memristor devices. In the paper authors show the verification of the IMPLY function by using Ni/HfO2/Si manufactured devices and laboratory measurements. The proper behavior of the IMPLY structure (2 memristors) has been shown. The paper also verifies the proper operation of a two-step IMPLY-based NAND gate implementation, showing the electrical behavior of the circuit in a cycling operation. A new procedure to implement a NAND gate that requires only one step is experimentally shown as well.

Temperature dependence of the resistive switching-related currents in ultra-thin high-k based MOSFETs

In this work, the temperature dependence of the resistive switching phenomenon in metal-oxide-semiconductor field-effect-transistor (MOSFETs) with an ultra-thin Hf-based high-k dielectric is studied through analysis of the gate and drain currents for the two dielectric conductivity states. These two different conductive states of the resistive switching have been associated with the dielectric breakdown (BD) and dielectric BD reversibility (R), respectively, and are related to the creation of a BD path through the dielectric that can be understood as a conductive filament. The results of the temperature dependence of the post-BD gate current are in agreement with those obtained from the study of the injected charge to recovery, which is a useful parameter with which to analyze the switch from the high to low conductivity state. The drain current in the MOSFETs for the two conductivity states, for different locations of the BD path along the channel (close to the source and close to the drain), and at several temperatures has also been studied. The results contribute to a better understanding of the resistive switching phenomenon in ultra-thin gate dielectrics. This contribution could be useful for the developing of models to describe BD reversibility.