Mirko Reissmann

Integrated circuit having a memory cell arrangement and method for reading a memory cell state using a plurality of partial readings

Method for testing a memory device, test unit for testing a memory device and memory device

Memory Device with Adaptive Sense Unit and Method of Reading a Cell Array

Nonvolatile memory device and method of programming the same

Method for setting a read voltage, and semiconductor circuit arrangement

Integrierter Schaltkreis mit einer Speicherzellenanordnung und Verfahren zum Lesen eines Speicherzellenzustands unter Verwendung einer Mehrzahl von Teil-Leseoperationen

An integrated circuit comprising a memory cell array and method of reading a memory cell state using a plurality of sub-read operations

Charge-trapping-memory device i.e. Nitride ROM, programming and deletion method, involves executing programming cycle as reference point that is shifted based on wear-level determination, and executing testing process based on threshold

Integrierter Schaltkreis mit einer Speicherzellenanordnung und Verfahren zum Lesen eines Speicherzellenzustands unter Verwendung einer Mehrzahl von Teil-Leseoperationen An integrated circuit comprising a memory cell array and method of reading a memory cell state by using a plurality of sub-read operations

Halbleitereinrichtung mit adaptiver Leseeinheit und Verfahren zum Lesen eines Speicherzellenfeldes