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Mirko Reissmann

Qimonda

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Publication

Featured researches published by Mirko Reissmann.

Archive | 2008

Integrated circuit having a memory cell arrangement and method for reading a memory cell state using a plurality of partial readings

Roberto Ravasio; Detlev Richter; Gert Koebernik; Girolamo Gallo; Mirko Reissmann; Ramirez Xavier Veredas

Archive | 2005

Method for testing a memory device, test unit for testing a memory device and memory device

Marco Ziegelmayer; Detlev Richter; Andreas Kux; Mirko Reissmann

Archive | 2007

Memory Device with Adaptive Sense Unit and Method of Reading a Cell Array

Detlev Richter; Mirko Reissmann; Volker Zipprich-Rasch; Gert Köbernik; Uwe Augustin; Konrad Seidel; Andreas Kux; Hans Heitzer; Daniel-André Löhr; Sören Irmer

Archive | 2006

Nonvolatile memory device and method of programming the same

Konrad Seidel; Uwe Augustin; Gert Koebernick; Sören Irmer; Daniel-Andre Loehr; Volker Zipprich-Rasch; Mirko Reissmann

Archive | 2007

Method for setting a read voltage, and semiconductor circuit arrangement

Uwe Augustin; Gert Koebernik; Mirko Reissmann

Archive | 2009

Integrierter Schaltkreis mit einer Speicherzellenanordnung und Verfahren zum Lesen eines Speicherzellenzustands unter Verwendung einer Mehrzahl von Teil-Leseoperationen

Girolamo Gallo; Gert Köbernik; Roberto Ravasio; Mirko Reissmann; Detlev Richter; Ramirez Xavier Veredas

Archive | 2008

An integrated circuit comprising a memory cell array and method of reading a memory cell state using a plurality of sub-read operations

Girolamo Gallo; Gert Köbernik; Roberto Ravasio; Mirko Reissmann; Detlev Richter; Ramirez Xavier Veredas

Archive | 2008

Charge-trapping-memory device i.e. Nitride ROM, programming and deletion method, involves executing programming cycle as reference point that is shifted based on wear-level determination, and executing testing process based on threshold

Konrad Seidel; Uwe Augustin; Gert Koebernick; Sören Irmer; Daniel-Andre Loehr; Volker Zipprich-Rasch; Mirko Reissmann

Archive | 2008

Integrierter Schaltkreis mit einer Speicherzellenanordnung und Verfahren zum Lesen eines Speicherzellenzustands unter Verwendung einer Mehrzahl von Teil-Leseoperationen An integrated circuit comprising a memory cell array and method of reading a memory cell state by using a plurality of sub-read operations

Girolamo Gallo; Gert Köbernik; Roberto Ravasio; Mirko Reissmann; Detlev Richter; Ramirez Xavier Veredas

Archive | 2007

Halbleitereinrichtung mit adaptiver Leseeinheit und Verfahren zum Lesen eines Speicherzellenfeldes

Detlev Richter; Mirko Reissmann; Volker Zipprich-Rasch; Gert Köbernik; Uwe Augustin; Konrad Seidel; Kux Andreas; Hans Heitzer; Daniel-André Löhr; Sören Irmer

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Collaboration

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Detlev Richter

Infineon Technologies

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Gert Köbernik

Qimonda

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Uwe Augustin

Infineon Technologies

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Konrad Seidel

Infineon Technologies

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Sören Irmer

Qimonda

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Volker Zipprich-Rasch

Qimonda

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Daniel-André Löhr

Qimonda

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Girolamo Gallo

Qimonda

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Hans Heitzer

Qimonda

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Ramirez Xavier Veredas

Qimonda

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