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Dive into the research topics where Detlev Richter is active.

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Featured researches published by Detlev Richter.


international test conference | 1998

How we test Siemens Embedded DRAM Cores

Roderick Dr Mcconnell; Udo Möller; Detlev Richter

The techniques used to test Siemens Embedded DRAM Cores are described. Test Isolation and Design-For-Test logic is built in to the core interface, while external access and Algorithmic Pattern Generation are handled by a central Test Controller. All tests used for standard DRAMs can be applied to the DRAM cores, but only a subset of these are used for any given product.


international test conference | 2001

Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs

Zaid Al-Ars; A. J. van de Goor; Jens Braun; Detlev Richter

Temperature has proven to be an effective stress condition, commonly used to stress memory devices and to detect special types of failure mechanisms. In this paper a new approach is presented where temperature is used as a test parameter to increase the fault coverage of specific tests. This is done using defect injection and simulation of a memory model at different temperatures. The analysis presents new types of detection conditions for memories and evaluates the impact of temperature on these conditions.


asian test symposium | 2001

A memory specific notation for fault modeling

Zaid Al-Ars; A. J. van de Goor; Jens Braun; Detlev Richter

This paper shows the shortcomings of the current, generic notation for fault models and extends it to allow the description of fault models for DRAMs. The advantage is that the extended fault models can easily be translated into operation sequences and tests that detect the described fault. Examples are given to show that the new notation results in optimized, memory specific, tests that have a shorter run time for a given fault coverage.


design, automation, and test in europe | 2003

Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation

Zaid Al-Ars; Ad J. van de Goor; Jens Braun; Detlev Richter

Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection and electrical simulation. The new method shows how each stress should be applied to achieve a higher fault coverage of a given rest, based on an understanding of the internal behavior of the memory. In addition, results of a fault analysis study, performed to verify the new optimization method, show its effectiveness.


Archive | 2008

Memory Cell Arrangement and Method for Reading State Information From a Memory Cell Bypassing an Error Detection Circuit

Jan Gutsche; Michael Scheppler; Detlev Richter; Doris Keitel Schulz; Helmut Schwalm


Archive | 2005

Method for testing a memory device, test unit for testing a memory device and memory device

Marco Ziegelmayer; Detlev Richter; Andreas Kux; Mirko Reissmann


Archive | 2001

Method for testing the refresh device of an information memory

Detlev Richter; Wolfgang Spirkl


Archive | 2005

Semiconductor memory and method for operating a semiconductor memory comprising a plurality of memory cells

Detlev Richter; Konrad Seidel


Archive | 1999

Configuration of memory cells and method of checking the operation of memory cells

Roderick McConnell; Detlev Richter


Archive | 1999

Method of testing an integrated circuit having a memory and a test circuit

Detlev Richter; Roland Weigand

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