Mitchell R. LeRoy

A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology

The search for high speed, high bandwidth A/D converters is ongoing, and techniques to push the envelope are constantly being developed. In this paper an open loop, scalable, time-interleaved ADC architecture is presented, as well as a 60 GHz Colpitts oscillator. With the use of double-sampling, the timing skew requirements between channels is greatly relaxed, allowing sampling rates of up to 40 Gs/s at 4-bits of accuracy. This circuit is implemented using the IBM 8HP SiGe technology, with fT of 210 GHz. The performance of the 8HP ADC is validated by measurement. In addition, simulations with an experimental 8XP transistor model provided by IBM with a 350 GHz fT suggest that 30% more circuit speed is possible by just swapping the transistors.

A three-dimensional DRAM using floating body cell in FDSOI devices

This paper describes the capacitorless 1-transistor (1T) DRAMs exploits the floating body (FB) effect of Fully depleted (FD) SOI devices, where the transistor body is used as a charge storage node. A novel three-tier, 3D, 1T embedded DRAM is presented that can be vertically integrated with the microprocessor achieving low cost, high density on-chip main memory. A 394Kbits test chip is designed and fabricated in a 0.15um fully depleted SOI CMOS process. The measured retention time under holding conditions is higher than 10ms. In the continuous read mode, every read should be followed by a refresh. The test chip is designed to work with an access time of 50ns and operates at 10MHz.

Modeling and Analysis of an 80-Gbit/s SiGe HBT Electrooptic Modulator

We present a rigorous electrical and optical analysis of a strained and graded base SiGe Heterojunction Bipolar Transistor (HBT) electrooptic (EO) modulator. In this paper, we propose a 2-D model for a graded base SiGe HBT structure that is capable of operating at a data bit rate of 80 Gbit/s or higher. In this structure, apart from a polysilicon/monosilicon emitter (Width = 0.12 μm) and a strained SiGe graded base (Depth = 40 nm) , a selectively implanted collector (SIC) (Depth = 0.6 μm) is introduced. Furthermore, the terminal characteristics of this new device modeled using MEDICI are closely compared with the SiGe HBT in the IBM production line, suggesting the possibility of fast deployment of the EO modulator using established commercial processing. At a subcollector depth of 0.4 μm and at a base-emitter swing of 0 to 1.1 V, this model predicts a rise time of 5.1 ps and a fall time of 3.6 ps. Optical simulations predict a π phase shift length (Lπ) of 240.8 μm with an extinction ratio of 7.5 dB at a wavelength of 1.55 μm. Additionally, the tradeoff between the switching speed, Lπ and propagation loss with a thinner subcollector is analyzed and reported.

Carry Chains for Ultra High-Speed SiGe HBT Adders

Adder structures utilizing SiGe Hetero-junction Bipolar Transistor (HBT) digital circuits are examined for use in high clock rate digital applications requiring high-speed integer arithmetic. A 4-gate deep test structure for 32-bit addition using a 210 GHz fT process has been experimentally verified to operate with 37.5 ps delay or 26.7 GHz speed. The paper documents a unique blend of CML and ECL circuit innovations, which is needed to obtain this result. The chip is estimated to have a power-delay product of 109 ps-W at a device temperature of 85°C . A low power design is shown to have a power-delay product of 48 ps-W at 21.7 GHz. Speed-power trade-offs are explored through pure ECL logic and varying current. Additionally, with next generation SiGe HBTs, this work shows that 40 GHz is achievable at slightly above room temperature.

On the Performance of Lateral SiGe Heterojunction Bipolar Transistors With Partially Depleted Base

This paper discusses improvements to a lateral bipolar device capable of integration into the existing CMOS process flow. With the help of simulations, we demonstrate that the emitter transit time limits the cutoff frequency of a lateral bipolar device. We show that with the introduction of a heterojunction and a partially depleted base, we can decrease the emitter transit time and increase the current gain and the cutoff frequency (ft) of the device. For a balanced design, our simulations indicate an n-p-n device with an ft of 812 GHz and an fmax of 1.08 THz; and a p-n-p device with an ft of 635 GHz and an fmax of 1.15 THz. The collector current at cutoff frequency for both n-p-n and p-n-p devices is ~0.03 mA-roughly 100 times lower than commercial vertical heterojunction bipolar transistors.

Synthesis of Perfectly Causal Parameterized Compact Models for Planar Transmission Lines

Per-unit-length series impedance and shunt admittance are extracted from electromagnetic analysis of a transmission line at a few discrete frequencies. Compact models are synthesized from the per-unit-length extraction. The lumped models are then used to rapidly calculate characteristic impedance, effective dielectric constant, and RLGC parameters at all frequencies, including dispersion and loss. The resulting models are perfectly physically (i.e., speed of light) causal, a critical consideration for time-domain analysis. To demonstrate feasibility, the models are parameterized as a function of transmission linewidth. Total error is carefully quantified and is typically less than 1%. The process is demonstrated for several planar transmission lines. New concepts, ¿modal¿ and ¿environmental¿ sensitivity, are introduced and quantified.

High-Speed Reconfigurable Circuits for Multirate Systems in SiGe HBT Technology

In this paper, we discuss the advantages and opportunities presented by high-speed (> 50 GHz) reconfigurable integrated circuits and how they may drive reconfigurable systems applications, such as software-defined radio, radar, and imaging. We propose silicon-germanium (SiGe) BiCMOS as an example technology that enables ultrafast reconfigurable systems and present several circuit designs based on SiGe heterojunction bipolar transistors (HBTs). We compare circuit designs between generations of IBMs SiGe process, including a recent 9HP process featuring devices with a cutoff frequency (fT) of 300 GHz. We describe an architecture for an 8-b 80-Gs/s analog-to-digital converter (ADC) and a 48 × 48 cell field programmable gate array (FPGA), which provide powerful solutions for useful functions, such as digital signal processing (DSP) and polyphase filtering. Other circuit concepts are described, including a voltage-controlled oscillator (VCO) with a tuning range of 26 GHz and a high-performance (80 Gb/s) crossbar switch, which provide utility in reconfigurable system applications. Measured results from fabricated implementations of these described systems are presented. We comment on future prospects of these systems and examine an emerging lateral bipolar device (fT 1/4 825 GHz) having 100x less power consumption than conventional vertical HBTs.

140 Gb/s Serializer Using Clock Doublers in 90 nm SiGe Technology

Many design challenges exist in achieving high frequency clocking for high-speed applications. This paper describes a new clock distribution technique and clocking approach with the use of clock doublers in close proximity to sub-circuits to achieve higher data rates, and in many cases, reduce design complexity and power in serializers. A half-rate 4:1 serializer using this unique frequency doubling clock distribution technique has been implemented in a 90 nm BiCMOS process. The design includes a 210-1 pattern length LFSR with phase shifting logic as the testing circuit and a high bandwidth cascoded output driver. The chip has the dimensions of 1.8 × 2.2 mm 2 and consumes 5.78 W from a -3.4 V supply voltage at 140 Gb/s.

Thermal Modeling of 3-D Stacked DRAM Over SiGe HBT BiCMOS CPU

We have previously evaluated the feasibility of a serial code accelerator core with 3-D DRAM stacked on the core operating at high frequencies. While operating at such high frequencies (>24 GHz), there are concerns with removing heat from the 3-D stack. We propose the use of thin diamond sheets, which have high thermal conductivity, as a heat spreader by bonding it close to the processor core substrate and memory stacks. We show, through thermal modeling using COMSOL finite-element analysis tools, the feasibility of diamond as an effective heat spreader in a processor-memory 3-D stack.

Design of High-Speed Register Files Using SiGe HBT BiCMOS Technology

The time needed for processing serial code in programs has become the performance bottleneck of multicore computer systems according to Amdahls law. A high-speed clock rate processor is essential for processing this serial code. The register file is the core component in high-performance processors due to its direct impact on the cycle per instruction of the CPU. This brief presents the design of a high-speed register file used in high-clock-rate processors that use SiGe heterojunction bipolar transistor BiCMOS technology and current-mode logic-style circuits. The demonstrated register file is fabricated in IBM BiCMOS 0.13- μm technology and has a measured frequency of 18.4 GHz. The highest operational frequency has been simulated at 27 GHz using layout extracted simulation at 85 °C after adopting improved pipeline structures. Further advanced technology (8XP) can improve the speed or reduce the power consumption of this register file.