Philip Jacob

Predicting the performance of a 3D processor-memory chip stack

We are exploring a 3D processor-memory stack for use with the message passing interface (MPI). The communication among processors in huge servers wastes several thousands of cycles. Most of these wasted cycles do not come from the communication link among the processors across the system, but rather in handling the message packets. A processor that could handle this message packing and communication at a much faster rate could significantly increase this tasks efficiency and thus increase the utilization of such supercomputers, currently a very low 1%. However, at such high clock rates, the memory wall would become a significant problem. Tackling this problem requires innovative technologies, such as 3D memories, which alleviate some problems with long on-chip interconnects. The importance of interconnection wires to circuit performance is on a chip. The need for shorter interconnection delays suggests shorter interconnection wires. Shorter interconnections are more likely in 3D architectures than in equivalent 2D systems. This article explores the advantages of 3D in a processor-memory stack system. We conducted simulations using simple tools like Dinero IV and the cache access and cycle time information (Cacti) to evaluate the performances of various memory architectures.

Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks

Three-dimensional chip (3-D) stacking technology provides a new approach to address the so-called memory wall problem. Memory processor chip stacking reduces this memory wall problem, permitting faster clock rates (with suitable processor logic) or permitting multicore access to shared memory using a large number of vertical vias between tiers in the stack, for ultrawide bit path transfer of data and address information to and from various levels of cache. Although a limited amount of parallel access is possible using conventional two-dimensional (2-D) chip memory-processor approaches, 3-D memory-processor stacking greatly extends this to much larger capacity memories. We evaluate high-clock-rate processors as well as shared memory processors with a large number of cores. Various architectural design options to reduce the impact of the memory wall on the processor performance are explored and validated through simulations. Certain architectural features can be implemented in a 3-D chip, such as an ultrawide, ultrashort vertical bus with low parasitic resistance and the elimination of conventional electrostatic discharge, and packaging parasitics required in multiple package 2-D solutions. The objective is to reduce the clocks per instruction figure of merit for high clock speeds in order to deliver significant performance levels. High-clock-rate processors can be designed with SiGe heterostructure bipolar transistors to obtain processors operating on the order of 16 or 32 GHz.

A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology

The search for high speed, high bandwidth A/D converters is ongoing, and techniques to push the envelope are constantly being developed. In this paper an open loop, scalable, time-interleaved ADC architecture is presented, as well as a 60 GHz Colpitts oscillator. With the use of double-sampling, the timing skew requirements between channels is greatly relaxed, allowing sampling rates of up to 40 Gs/s at 4-bits of accuracy. This circuit is implemented using the IBM 8HP SiGe technology, with fT of 210 GHz. The performance of the 8HP ADC is validated by measurement. In addition, simulations with an experimental 8XP transistor model provided by IBM with a 350 GHz fT suggest that 30% more circuit speed is possible by just swapping the transistors.

A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration

Slow cache memory systems and low memory bandwidth present a major bottleneck in performance of modern microprocessors. 3-D integration of processor and memory subsystems provides a means to realize a wide data bus that could provide a high bandwidth and low latency on-chip cache. This paper presents a three-tier, 3-D 192-kB cache for a 3-D processor-memory stack. The chip is designed and fabricated in a 0.18 m fully depleted SOI CMOS process. An ultra wide data bus for connecting the 3-D cache with the microprocessor is implemented using dense vertical vias between the stacked wafers. The fabricated cache operates at 500 MHz and achieves up to 96 GB/s aggregate bandwidth at the output.

Carry Chains for Ultra High-Speed SiGe HBT Adders

Adder structures utilizing SiGe Hetero-junction Bipolar Transistor (HBT) digital circuits are examined for use in high clock rate digital applications requiring high-speed integer arithmetic. A 4-gate deep test structure for 32-bit addition using a 210 GHz fT process has been experimentally verified to operate with 37.5 ps delay or 26.7 GHz speed. The paper documents a unique blend of CML and ECL circuit innovations, which is needed to obtain this result. The chip is estimated to have a power-delay product of 109 ps-W at a device temperature of 85°C . A low power design is shown to have a power-delay product of 48 ps-W at 21.7 GHz. Speed-power trade-offs are explored through pure ECL logic and varying current. Additionally, with next generation SiGe HBTs, this work shows that 40 GHz is achievable at slightly above room temperature.

Reconfigurable 40 GHz BiCMOS uniform delay crossbar switch for broadband and wide tuning range narrowband applications

A wide-band crossbar switch configured as a non-blocking signal router can be used in various applications that need reconfigurable digital or analog cross connections such as network switches, CPU-memory connecting modules and wide tuning range radar switches. Current mode logic using IBM 8HP SiGe heterojunction bipolar transistors having f T s of 210 GHz and a symmetrical signal path design are employed to make a 40 GHz crossbar switch capable of 80 Gb/s transmission with a fast reconfiguration time of 160 ps. A unique feature of this crossbar is that the delay through any path in the switch is constant. The f T of IBMs 8XP SiGe model is 350 GHz, which allows for faster circuits than the 8HP technology. The crossbar switch using IBMs 8XP kit is simulated to predict further performance improvement to 50 GHz (100 Gb/s for binary signals). To demonstrate the maximum operating speed, the crossbar switch is tested as a 40 GHz phase router for a phased array antenna system. The measured output of the crossbar switch is a 38.8 GHz sine wave with the selected phase delay. The phase noise of the output signal is -88.3 dBc/Hz for an input whose phase noise is -98 dBc/Hz at 1 MHz offset. Using a 2.5 V supply, the 8HP crossbar switch consumes 2.2-5.7 W depending on the number of active channels. The power dissipation of the crossbar switch can be reduced by about 70% with the same performance by using the 8XP kit.

Thermal Modeling of 3-D Stacked DRAM Over SiGe HBT BiCMOS CPU

We have previously evaluated the feasibility of a serial code accelerator core with 3-D DRAM stacked on the core operating at high frequencies. While operating at such high frequencies (>24 GHz), there are concerns with removing heat from the 3-D stack. We propose the use of thin diamond sheets, which have high thermal conductivity, as a heat spreader by bonding it close to the processor core substrate and memory stacks. We show, through thermal modeling using COMSOL finite-element analysis tools, the feasibility of diamond as an effective heat spreader in a processor-memory 3-D stack.

Correction to “A 40 GS/s Time Interleaved ADC Using SiGe BiCMOS Technology”

In the above titled paper (ibid., vol. 45, no. 2, pp. 380-390, Feb. 10), a mistake in a value used in the calculation of the third harmonic in equation (1) was discovered by Dr. Kilic. The correct value is presented here.

A 3-tier, 3-D FD-SOI SRAM macro

Three dimensional memory systems has been argued as a potential pathway in solving the ever growing difference between comparative speeds of CPU and memory systems. In this paper, we describe a three-tier, three-dimensional SRAM macro that has been designed and fabricated in a 0.18 um FD-SOI CMOS technology. 3D stacking is found to improve wire latency as compared to planar memory structure although the reduction is not enough to have a significant effect on access time of the memory. It is argued that the major performance benefit obtained by 3D integration is in term of very wide data bus that can be realized much more easily with 3D structures as compared to 2D memories.