Mitchell Reid

A Fully Integrated 0.13

This paper presents the first low-IF fully integrated receiver for DBS satellite TV applications realized in 0.13 mum CMOS. A wideband ring oscillator based frequency synthesizer having a large frequency step was used to downconvert a cluster of channels to a coarsely defined low-IF frequency, while the second downconversion to baseband was performed in the digital domain. Eliminating the oscillator inductors reduced the parasitic magnetic coupling from the digital core, allowing a single-chip integration of the sensitive tuner and the noisy digital demodulator. A significant die area reduction was achieved by using a single oscillator to cover the entire satellite TV spectrum, while a noise attenuator was cascaded with the PLL loop filter to reduce the equivalent tuning gain. The low-IF architecture allowed a discrete-step AGC that improves both tuner noise and linearity performance. Tuner gain and IF corner frequency were calibrated using replica ring oscillators that are tuned up to the onset of oscillations. The tuner specifications include: 90 dB gain range, 9 dB noise figure at max gain, +25 dBm IIP3 at min gain, 1.3degrms integrated phase noise, les50 dBc spurs, 0.7 W power consumption from dual 1.8/3.3-V supplies, and 1.8times1.2 mm 2 die area

\mu{\hbox {m}}

The proposed DDFS-driven mixing-DAC consists of several parallel-connected Gilbert cells driven directly by the binary and thermometer DDFS data compromise between power-dissipation and harmonic-rejection performance is achieved with 5b binary LSBs and 5b thermometer MSBs segmented mixing-DAC. The 2.8-to-3.2 GHz DDFS sampling frequency is selected such that it provides in excess of two samples per cycle up to 1 GHz, while the LO sampling spurs (fsplusmnfL0) are always outside the receiver desired frequency band. It is dynamically adjusted for each received channel to minimize in-band DDFS induced spurs.

CMOS Low-IF DBS Satellite Tuner Using Automatic Signal-Path Gain and Bandwidth Calibration

A digital low-IF receiver for satellite TV applications was realized in 110 nm CMOS taking advantage of high speed and moderate resolution ADCs and high digital processing power available in nanometer CMOS. A discrete gain step signal path and a digital power level measurement together with a digital AGC loop implementation resulted in lower receiver area and power and a smaller noise figure penalty. Image rejection in excess of 50 dB was achieved by using a continuous digital I/Q mismatch correction engine that relaxes the matching requirements on the analog front-end and thus reduces the occupied die area. A dynamic digital clock frequency management algorithm was implemented to avoid receiver de-sensitization due to digitally coupled in-band spurs. SoC specifications include: 0.2 dB implementation loss, <1.3degrms integrated phase noise,<-50 dBc spurs, <0.2 s channel acquisition time, 1.2 W power dissipation from a dual 1.8/3.3 V supply and 1.8 x 4.8 mm2 die area.