M. Chennam

A Fully Integrated 0.13

This paper presents the first low-IF fully integrated receiver for DBS satellite TV applications realized in 0.13 mum CMOS. A wideband ring oscillator based frequency synthesizer having a large frequency step was used to downconvert a cluster of channels to a coarsely defined low-IF frequency, while the second downconversion to baseband was performed in the digital domain. Eliminating the oscillator inductors reduced the parasitic magnetic coupling from the digital core, allowing a single-chip integration of the sensitive tuner and the noisy digital demodulator. A significant die area reduction was achieved by using a single oscillator to cover the entire satellite TV spectrum, while a noise attenuator was cascaded with the PLL loop filter to reduce the equivalent tuning gain. The low-IF architecture allowed a discrete-step AGC that improves both tuner noise and linearity performance. Tuner gain and IF corner frequency were calibrated using replica ring oscillators that are tuned up to the onset of oscillations. The tuner specifications include: 90 dB gain range, 9 dB noise figure at max gain, +25 dBm IIP3 at min gain, 1.3degrms integrated phase noise, les50 dBc spurs, 0.7 W power consumption from dual 1.8/3.3-V supplies, and 1.8times1.2 mm 2 die area

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A low-IF fully integrated tuner for DBS satellite TV applications has been realized in 0.13-mum CMOS. A wideband ring oscillator-based frequency synthesizer having a large frequency step was used to downconvert a cluster of channels to a sliding low-IF frequency, while the second downconversion to baseband was performed in the digital domain. Eliminating the inductors and using a small-area oscillator has reduced both the parasitic magnetic and substrate coupling, allowing single-chip integration of the sensitive tuner and the noisy digital demodulator. A significant reduction in die area was achieved by using a single oscillator to cover the entire satellite TV spectrum, while a noise attenuator was cascaded with the PLL passive loop filter to reduce the equivalent VCO tuning gain. This improves PLL noise and spur performance and allows the on-chip integration of the loop filter. The digital low-IF tuner allows the use of a discrete step AGC loop that results in lower noise figure and higher linearity. Automatic signal path gain and bandwidth digital calibration was realized using replica ring oscillators. Tuner specifications include: 90 dB gain range, 10 dB noise figure at max gain, +25dBm IIP3 at min gain, 1.3deg rms integrated phase noise, <-50dBc spurs, 0.5-W power consumption from dual 1.8/3.3-V supplies, and 1.8times1.2 mm2 die area

CMOS Low-IF DBS Satellite Tuner Using Automatic Signal-Path Gain and Bandwidth Calibration

The first low-IF fully-integrated tuner for DBS satellite TV applications was realized in 0.13 mum CMOS. A wideband ring oscillator based frequency synthesizer having a large frequency step was used to down-convert a cluster of channels to a coarsely defined low-IF frequency, while the second down-conversion to baseband was performed in the digital domain. Eliminating the oscillator inductors has reduced the parasitic magnetic coupling, allowing a single-chip integration of the sensitive tuner and the noisy digital demodulator. A significant die area reduction was achieved by using a single oscillator to cover the entire satellite TV spectrum, while a noise attenuator was cascaded with the PLL loop filter to reduce the equivalent tuning gain

A Fully Integrated 0.13-

A digital low-IF satellite TV tuner-demodulator SoC was realized in 0.13 mum CMOS using low power 200 MS/s eight bit pipeline ADCs. A discrete-steps delayed AGC loop using FET switched-resistors resulted in a 10 dB noise figure at max gain and +25 dBm IIP3 at min gain. The image rejection correction is continuously performed in the digital domain using an inverse gain and phase mismatch adjustment. A FFT engine was used for carrier/symbol rate estimation and channel blind scanning. SoC specifications include: 0.2 dB implementation loss, <1.3degrms integrated phase noise,<-50dBc spurs, <0.2s channel acquisition time, 1.2 W power dissipation from a dual 1.8/3.3V supply and 1.8 x 4.8 mm2 die area.

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A low-IF satellite TV demodulator front-end for single-chip receiver SoC was realized in 0.13 mum CMOS using a low-power 0.25mm2 8b time interleaved pipeline ADC. A 250MS/s conversion rate was achieved by sharing the sample-and-hold amplifier (SHA) between two time interleaved ADCs having eight 1.5b cascaded stages. The full-rate SHA uses a feed-forward source follower to speed-up the settling by pre-charging the amplifier output at the voltage level sampled at its input. The ADC area was reduced by sharing the operational amplifiers between the time interleaved paths. The digital clock was generated with a sampled switched-capacitor loop filter PLL which reduces both reference and supply injected spurs. ADCs specifications include: INL plusmn2LSB, DNL plusmn0.5LSB, SFDR greater than 59dB, 35mW power dissipation, while the PLL achieves <20pspp total jitter and <-60dBc spurs.

m CMOS Digital Low-IF DBS Satellite Tuner Using a Ring Oscillator-Based Frequency Synthesizer

A first low-IF fully-integrated tuner for DBS satellite TV applications was realized in 0.13 mum CMOS. A wide bandwidth, ring oscillator integer-N frequency synthesizer having a large frequency step was used to down-convert a cluster of channels to a coarsely defined low-IF frequency, while the second down-conversion to base band was performed in the digital domain. Eliminating the oscillator inductors has reduced the parasitic magnetic coupling from the digital circuitry, allowing single-chip tuner-demodulator integration

A fully-integrated 0.13/spl mu/m CMOS low-IF DBS satellite tuner using a ring oscillator based frequency synthesizer

A digital low-IF receiver for satellite TV applications was realized in 110 nm CMOS taking advantage of high speed and moderate resolution ADCs and high digital processing power available in nanometer CMOS. A discrete gain step signal path and a digital power level measurement together with a digital AGC loop implementation resulted in lower receiver area and power and a smaller noise figure penalty. Image rejection in excess of 50 dB was achieved by using a continuous digital I/Q mismatch correction engine that relaxes the matching requirements on the analog front-end and thus reduces the occupied die area. A dynamic digital clock frequency management algorithm was implemented to avoid receiver de-sensitization due to digitally coupled in-band spurs. SoC specifications include: 0.2 dB implementation loss, <1.3degrms integrated phase noise,<-50 dBc spurs, <0.2 s channel acquisition time, 1.2 W power dissipation from a dual 1.8/3.3 V supply and 1.8 x 4.8 mm2 die area.

A Single-chip DBS Tuner-Demodulator SoC using Discrete AGC, Continuous I/Q Correction and 200MS/s Pipeline ADCs

A fully-integrated digital low-IF DVB-S/DVB-S2 satellite TV tuner was realized in 0.13 μm CMOS. It uses a first analog down-conversion to a sliding low-IF, followed by digitization, a second digital mixing to baseband and digital channel selection. Performing more signal processing in the digital domain lead to a relaxation of the RF front-end specifications, allowing its CMOS implementation. The digital low-IF architecture provides a digital power estimation and allows the use of a discrete-step AGC loop that results in a lower noise and linearity degradation in comparison with continuous AGC loops. Digital calibration is used throughout the DVB tuner, minimizing the gain variation over corners and relaxing the noise and linearity constraints. Partitioning the DVB-S2 receiver into a front-end tuner IC built in a mixed-signal CMOS process and a back-end demodulator and MPEG processor IC implemented in a straight digital CMOS process minimizes the receiver cost

Notice of Violation of IEEE Publication Principles 0.13μm CMOS DBS demodulator front-end using a 250MS/s 8 bit time interleaved pipeline ADC and a sampled loop filter PLL

A digital low-IF fully-integrated dual tuner for DVB-S2 satellite TV applications was realized in 0.11μm CMOS. It provides baseband digital I/Q outputs for a demodulator-on-host back-end processor. A wide bandwidth ring oscillator based frequency synthesizer having a large frequency step was used to down-convert a cluster of channels to a sliding low-IF frequency, while the second down-conversion to baseband was performed in the digital domain. The low-IF architecture allows a discrete AGC loop, while avoiding 1/f noise and DC offset issues. Eliminating the VCO tank inductors minimizes frequency pulling and parasitic coupling to front-end LNA, allowing the integration of a large digital core on the same die with the sensitive RF front-end.