Mitsuru Kurihara

Automated mass production line for optical module using passive alignment technique

Since the growth of fiber optic communications, extremely low cost optical modules have been expected to be realized. Particularly for the subscriber applications and local area networks (LANs), less than half of past module cost is required. In accordance with the spread of fiber optic transmission, higher volume manufacture is also needed. To attain both of low cost and high productivity, we developed passive alignment technique and optical coupling structure that is suitable for automatic assembly. We also developed automatic assemble equipment for producing several types of optical modules. To reduce optical module cost, it is important to cut down the assembly cost and expensive parts such as optical lens. The passive alignment technique brings us to realize easy assembly of modules and minimize the constructed components of optical coupling. Our mass production techniques include not only for optical coupling but also packaging of the module. We have several types of optical modules according to different fiber communication systems; there are laser modules, detector modules, optical interface modules that are integrated optical coupling and electrical circuit, and PLC (Planar Lightwave Circuit) modules that are integrated passive component. Basically all modules have same optical coupling structure and keep the design rules for automatic assembly. Accordingly, we can use the same equipment for the same assembly process. In this paper, we will introduce basic assembly process and our mass production line for optical coupling and packaging by using passive alignment technique.

125-µm-pitch × 12-channel “optical pin” array as I/O structure for novel miniaturized optical transceiver chips

We have developed an optical I/O structure using an array of optical pins for a chip-scale parallel optical module named an “optical I/O core.” The optical pin is a kind of vertical polymer waveguide, which is made from UV curable resins. The optimum shape and combination of resins for the optical pins were determined by ray-trace simulation. The numerical aperture (NA) of the developed optical pins is more than 0.4. A photolithographic technique was used to produce a 125-μm-pitch × 12-channel optical pin array. The coupling losses between a GI-50 multi-mode optical fiber (MMF) and the optical pins for a receiver (RX) and transmitter (TX) were 0.41 dB and 2.3 dB, respectively. Wide coupling tolerance of more than 25 μm was also obtained when the allowable excess loss was 0.5 dB. Furthermore, clear eye diagrams were obtained for 25-Gbps back-to-back transmission by using the optical I/O cores with the optical pins and GI-50 MMF.

A 400 Gbps backplane switch with 10 Gbps/port optical I/O interfaces

A 400 Gbps backplane switch was developed with low-cost, small-size, 8-channels 10 Gbps/port optical I/O and a SiGe Bi-CMOS switch LSI on a 60x60-mm2 BGA package. It indicates the applicability of backplane switch for high throughput backplane interconnections.

A 25-Gb/s 5 × 5 mm 2 Chip-Scale Silicon-Photonic Receiver Integrated With 28-nm CMOS Transimpedance Amplifier

We have developed a 5 × 5 mm2 compact silicon-photonic receiver with a 28-nm CMOS transimpedance-amplifier (TIA) chip. The receiver chip was designed using a photonics-electronics convergence design technique for the realization of high-speed and high-efficiency operation because the interfaces of the optical and electrical components greatly influence the receiver characteristics. Optical pins were used to obtain easy optical alignment between the multimode fibers and the germanium photodetectors. An aluminum stripline between the PD and the TIA enhanced the 3-dB bandwidth because its characteristic impedance is greater than the TIA input impedance. Coplanar waveguides (CPWs) on the etched SOI wafer achieved a low insertion loss because the overlap between the electric fields of the CPWs and the silicon layer was reduced. We demonstrated 25-Gb/s error-free operation at both 25 and at 85 °C. The minimum sensitivities and power consumptions of the receivers were -11.0 dBm and 2.3 mW/Gb/s at 25 °C and -10.2 dBm and 2.5 mW/Gb/s at 85 °C, respectively. These results show that our receiver can be applied for practical use at high temperatures.

Tunable Lasers Based on Silica Waveguide Ring Resonators

We developed a hybrid integrated tunable laser based on waveguide ring resonators using passive alignment technology. A compact chip having a wavelength locker, stable high output power and excellent mass-productivity was achieved.

A 400Gbps backplane switch with 10Gbps/port optical I/O interfaces based on OIP (optical interconnection as IP of a CMOS library)

A 400 Gbit/s backplane switch was developed with a low-cost, small-size, 8-channel 10 Gbit/s/port optical I/O and a SiGe Bi-CMOS switch LSI on a 60/spl times/60-mm-square BGA package. It indicates the applicability of OIP for high throughput backplane interconnections.

Opto-electronics packaging techniques for interconnection

There is a dilemma in choosing between high density packaging and low loss transmission line. Though the LSI circuit and packaging become high density, the wiring on the printed wire board (PWB) becomes wider over 10 Gbit transmission. This paper introduces opto-electronics packaging techniques which aims to solve the problem of optical interconnection dilemma.

Optical I/O core transmitter with high tolerance to optical feedback using quantum dot laser

We discuss an isolator-free Si-photonics transmitter with a quantum-dot laser. A high tolerance to optical feedback of -30-dB against near-end reflections was successfully achieved. Furthermore, we also demonstrated the error-free operation of an optical I/O core at 25 Gbps.

Chip-scale packaging of hybrid-integrated Si photonic transceiver: Optical I/O core

A chip-scale package structure for Si photonic optical transceivers has been developed. The foot print of the transceiver is 5 mm × 5mm. By using an optical pin array and glass interposer with through-glass vias (TGVs), high density optical and electrical I/O interfaces are configured on one side of the package. The optical pin acts as a vertical waveguide or spot-size converter (SSC). The combination of the optical pin and the O-band multimode transmission provides large misalignment tolerance for the optical interface. The developed optical transceiver has a high degree of usability for various applications, such as multi-chip modules and active optical cables, and is called “optical I/O core.” The optical I/O core demonstrated 25 Gbps/ch error-free operation over a 300-m multimode fiber. The optical I/O core is a promising solution for relieving the I/O bottleneck in high-bandwidth inter-chip data transmission.

25-Gbps 5×5 mm chip-scale silicon-photonic receiver integrated with 28-nm CMOS transimpedance amplifier

We have developed a compact silicon-photonic receiver integrated with a CMOS transimpedance amplifier (TIA) chip and demonstrated 25-Gbps error-free operation. A minimum sensitivity of-9.7 dBm and a consumption power of 2.3 mW/Gbps were obtained.