Yasuhiko Hagihara

A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications

A read-static-noise-margin-free SRAM cell consists of seven transistors, several of which are low-V, NMOS transistors used to achieve both low-V/sub dd/ and high-speed operation. A 64 kb SRAM macro is fabricated in 90 nm CMOS technology. Both a minimum V/sub dd/ of 440 mV and a 20 ns access time with a 0.5 V supply are obtained.

Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit

We redefine write margin in order to be able to quantify the effect of both PVT variation and write-margin improvement. A write-margin monitoring circuit based on this definition is implemented in a 90nm CMOS process. This circuit can be applied to an SRAM power supply circuit to improve the write margin

A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP) ULSI

The first single-chip 64-b vector-pipelined processor (VPP) ULSI is described. It executes vector operations indispensable to high-speed scientific computation. The VPP ULSI attains a 200-MFLOPS peak performance at a 100-MHz clock frequency. This extremely high performance is made possible by the integration on the VPP of a 64-b five-stage pipelined adder/shifter, a 64-b five-stage pipelined multiplier/divider/logic operation unit, and a 40-kb register file. Various new high-speed circuit techniques have been also developed for 100-MHz operations. The chip, which was fabricated with a 0.8- mu m BiCMOS and triple-layer metallization process technology, has a 17.2-mm*17.3-mm area and contains about 693 K transistors. It consumes 13.2 W at a 100-MHz clock frequency with a single 5-V power supply. >

A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations

We have developed a circuit for determining an optimal supply voltage, VOPT, for which energy consumption will be minimized in devices suffering from high-leakage. This VOPT is determined on the basis of a trade-off between power consumption and operation time. Experimental results with a 90-nm CMOS device indicate that the proposed circuit successfully determines VOPT with high accuracy. VOPT operations with power gating at 40 MHz, and where VDD = 0.67 V, results in an energy reduction of 52.8% over that achieved with DVFS alone at 5 MHz (1/20 of maximum operational frequency). Further, we propose a scheme for suppressing determination error, one that results in voltage error of less than 50 mV.

Monitoring scheme for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

This paper describes a newly developed monitoring scheme for minimizing power consumption by means of supply voltage V/sub DD/ and threshold voltage V/sub TH/ dynamic control in active and standby modes. In the active mode, on the basis of delay monitoring results, either V/sub DD/ control or V/sub TH/ control is selected to avoid any oscillation problem between them. Switching current I/sub SW/ and leakage current I/sub LEAK/ are monitored, and V/sub TH/ is adjusted so as to maintain that ratio known to indicate minimum power consumption. In the standby mode, the precision of optimum body bias monitoring is improved by taking into consideration the effects of lowered V/sub DD/ and gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that the proposed scheme results in successful I/sub SW//I/sub LEAK/ ratio maintenance and successful detection of optimum body bias conditions (I/sub OFF/ = I/sub SUB/ (= GIDL + I/sub GB/)) to within 20% of actual minimum leakage current values.

A 25-Gb/s 5 × 5 mm 2 Chip-Scale Silicon-Photonic Receiver Integrated With 28-nm CMOS Transimpedance Amplifier

We have developed a 5 × 5 mm2 compact silicon-photonic receiver with a 28-nm CMOS transimpedance-amplifier (TIA) chip. The receiver chip was designed using a photonics-electronics convergence design technique for the realization of high-speed and high-efficiency operation because the interfaces of the optical and electrical components greatly influence the receiver characteristics. Optical pins were used to obtain easy optical alignment between the multimode fibers and the germanium photodetectors. An aluminum stripline between the PD and the TIA enhanced the 3-dB bandwidth because its characteristic impedance is greater than the TIA input impedance. Coplanar waveguides (CPWs) on the etched SOI wafer achieved a low insertion loss because the overlap between the electric fields of the CPWs and the silicon layer was reduced. We demonstrated 25-Gb/s error-free operation at both 25 and at 85 °C. The minimum sensitivities and power consumptions of the receivers were -11.0 dBm and 2.3 mW/Gb/s at 25 °C and -10.2 dBm and 2.5 mW/Gb/s at 85 °C, respectively. These results show that our receiver can be applied for practical use at high temperatures.

Floating-point datapaths with online built-in self speed test

This paper describes floating-point (FP) datapaths developed for graphics and simulation applications. The datapaths are fabricated using 0.35 /spl mu/m CMOS technology and embedded in a 125 MHz, 291 MFLOPS vector pipelined processor for use in supercomputers. A new online test technique has been developed for the purpose of improving reliability under actual operating conditions. The technique makes it easy to detect not only static faults but also delay faults, which has traditionally been difficult.

A 250 MHz CMOS floating-point divider with operand pre-scaling

High performance floating-point (FP) dividers are essential arithmetic units for graphics applications and simulations, and various algorithms and implementation techniques have been proposed. Using a 0.25 /spl mu/m CMOS technology, we have developed an FP divider, which supports IEEE-754 single-precision and double-precision formats. By using conventional static CMOS logic and (a) a radix-4 SRT algorithm (from the initials of Sweeny, Robertson and Tocher, who developed this algorithm at the same time) with a maximally redundant digit set, (b) a partially nonredundant remainder scheme and (c) a simple operand pre-scaling; the divider can calculate 4 quotient digits/cycle at over 250 MHz with a 2.5 V power supply.

Floating point datapaths with on-line built-in self speed test

This paper describes floating point (FP) datapaths developed for graphics and simulation applications. The datapaths are fabricated using 0.35 /spl mu/m CMOS technology and embedded in a 125 MHz, 290 MFLOPS vector pipelined processor for use in supercomputers. A new on-line test technique has been developed for the purpose of improving reliability under actual operating conditions. The technique makes it easy to detect not only static faults but also delay faults, which have traditionally been difficult to detect.

An Optimal Supply Voltage Determiner Circuit for Minimum Energy Operations

We have developed a circuit for determining an optimal supply voltage, VOPT for which energy consumption in circuit operations will be minimized in devices suffering from high-leakage. This VOPT is determined on the basis of a trade-off between power consumption and delay time. Experimental results with a 90-nm CMOS device indicate that the proposed circuit successfully determines VOPT within 3% of actual minimum energy consumption. VOPT operations with power gating at 40 MHz, and where VDD=0.67 V, results in an energy reduction of 52.8% over that achieved with DVFS alone at 5 MHz (1/20 of maximum operational frequency).