Mitsutaka Morimoto

Process of forming electrodes and interconnections on silicon semiconductor devices

A process of forming electrodes and interconnections in a silicon semiconductor device comprises the steps of forming an insulating film on a silicon substrate, defining an opening in the insulating film, depositing a layer of metal having a high melting point on the insulating film, implanting ions to mix an interface between the metal layer and the silicon substrate, heating the construction in a temperature in the range of from 400 to 650 degrees Celsius to form a silicide of the metal layer in the opening, and selectively etching away an unreacted metal layer so as to self-align the silicide metal layer with the opening. The silicide metal layer is then annealed in a non-reducing gas atmosphere at a temperature ranging from 800 to 1,100 degrees Celsius.

A Self-Aligned Mo-Silicide Formation

Mo-silicides, formed by a new technique combining ion implantation through metal film (ITM) to induce metal/Si interface mixing and also to form doped layers with appropriate subsequent annealings, were found to have excellent properties in film uniformity and self-aligned formation for exposed Si areas (contact holes). These excellent silicidation properties in the ITM technique were also confirmed for patterned poly-Si silicidation. Lateral silicide growth out of contact holes, usually observed in silicidation using mere thermal reaction of refractory-metal/Si structures, was markedly suppressed in the ITM silicidation.

Planarized Via-Hole Filling with Molybdenum by Bias Sputtering

Via-hole filling and surface planarization (planarized via-hole filling) were achieved by molybdenum (Mo) bias sputtering under high (~80%) resputtering, i.e., high (~ -600 V) substrate bias voltage, conditions. It was shown that Mo redeposition on the via-hole side walls from the via-hole bottom in the early film deposition stages and Mo redeposition on the bottom from the side walls in the latter film deposition stages played an important role in planarized via-hole filling. Planarized via-hole filling, without sputter-induced damage, was achieved by changing the substrate bias in two steps. The first step was thin layer deposition at a lower substrate bias, to protect the Si substrate surface from severe sputter-etching. The second step was planarized via-hole filling at a higher substrate bias.