Tohru Mogami

The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling

This paper presents a new reliability scaling scenario for CMOS devices with direct-tunneling ultra-thin gate oxide. Device degradation due to bias-temperature instability (BTI) was studied. First, the stress voltage dependence of BTI results indicate that the direct-tunneling electron and/or hole transport does not play a major role in the degradation mechanism. Secondly, it was found that the threshold voltage change caused by BTI for the PMOSFET limits the device lifetime, which is shorter than that defined by hot-carrier induced degradation for the NMOSFET. It originates from the difference of supply voltage dependence between BTI and hot-carrier degradation.

Bias temperature instability in scaled p/sup +/ polysilicon gate p-MOSFET's

The bias temperature instability in surface-channel p/sup +/ polysilicon gate p-MOSFETs was evaluated. It was found that a large negative threshold voltage shift (/spl Delta/V/sub th,BT/) is induced by negative bias temperature (BT) stress in short-channel p/sup +/ polysilicon gate p-MOSFETs. This Vth shift, which depends on the gate length of p-MOSFETs, is a new degradation mode. In this degradation, the negative /spl Delta/V/sub th,BT/ increases significantly with a reduction in the gate length. It was shown that this is because of the local degradation of the gate oxide near the gate edge. This degradation is caused by the electrochemical reaction between holes and oxide defects and it is enhanced by boron penetration through the gate oxide from p/sup +/-gate. For the bias temperature instability in p/sup +/-gate p-MOSFETs, sufficient care should be taken in scaled dual-gate CMOS devices.

A study of the threshold voltage variation for ultra-small bulk and SOI CMOS

This paper addresses the scalability of bulk CMOS, and the feasibility of intrinsic channel SOI (IC-SOI) CMOS, as an alternative to the bulk, in view of the threshold voltage (V/sub TH/) fluctuations. The impact of dopant-induced V/sub TH/ variations on bulk CMOS SRAM operation is evaluated using a newly proposed analytical method. It is estimated that the bulk SRAM performance will be seriously degraded as the channel length approaches 25-30 nm even if an elaborate redundancy scheme is used. For the IC-SOI FETs, instead of the dopant fluctuations, silicon thickness variation is a critical issue. However, systematic simulation results show that, by optimizing the FET design, the thickness-induced V/sub TH/ variations for both planar single gate and vertical double gate 25 mm IC-SOI FETs will be acceptable, assuming a reasonable thickness deviation range. Therefore, the IC-SOI CMOS is expected to be superior to the bulk counterpart at L=25 nm. It was also found that optimizing the back bias is necessary for suppressing the V/sub TH/ variations of the single gate IC-SOI FETs.

A dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film

A novel dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film is described. It is based on a new finding that threshold voltage (V/sub th/) depends on the concentration of nitrogen in the TiNx gate electrode. We found that a V/sub th/ shift as high as -110 mV is controlled by low-energy nitrogen-ion implantation (N I/I) into the titanium nitride film. By using this technology only for nMOSFETs, dual-metal gate CMOS devices are fabricated with a CMOS-process compatibility. A low V/sub th/ is achieved for both n- and pMOSFETs by combining N I/I and a low-doped channel structure.

Sub-10-nm planar-bulk-CMOS devices using lateral junction control

Sub-10-nm planar-bulk-CMOS devices were clearly demonstrated by a lateral source/drain (S/D) junction control using the precisely-controlled gate-electrode, shallow source/drain extensions (SDE) and steep halo. Good cut-off characteristics were observed for n/pMOSFETs with the gate length of 5 nm at 0.4 V for the first time.

Direct Measurement of Correlation Between SRAM Noise Margin and Individual Cell Transistor Variability by Using Device Matrix Array

Noise margin, characteristics of six individual cell transistors, and their variability in static random-access memory (SRAM) cells are directly measured using a special device-matrix-array test element group of 16-kb SRAM cells, and the correlation between the SRAM noise margin and the cell transistor variability is analyzed. It is found that each cell shows a very different supply voltage Vdd dependence of the static noise margin (SNM), and this scattered Vdd dependence of the SNM is not explained by the measured threshold voltage Vth variability alone, indicating that the circuit simulation taking only the Vth variability into account will not predict the SRAM stability precisely at low supply voltage.

45-nm gate length CMOS technology and beyond using steep halo

45-nm CMOS devices with a steep halo using a high-ramp-rate spike annealing (HRR-SA) are demonstrated with drive currents of 697 and 292 /spl mu/A//spl mu/m for an off current less than 10 nA//spl mu/m at 1.2 V. For an off current less than 300 nA//spl mu/m, 33-nm pMOSFETs have a high drive current of 403 /spl mu/A//spl mu/m at 1.2 V. In order to fabricate a steeper halo than these MOSFETs, a source/drain extension (SDE) activation using the HRR-SA process was performed after a deep source/drain (S/D) formation. By using this sequence defined as a reverse-order S/D formation, 24-nm nMOSFETs are achieved with a high drive current of 796 /spl mu/A//spl mu/m for an off current less than 300 nA//spl mu/m at 1.2 V.

High mobility MISFET with low trapped charge in HfSiO films

MISFETs with HfSiO (EOT:1.8 nm) gate insulator have been reached high Ion (95%) and low gate leakage current (1/100) against SiO/sub 2/ gate film. This was achieved by the suppression of the remote Coulomb scattering, caused by the electron traps in the HfSiO gate stack. It was experimentally confirmed that less than 3/spl times/10/sup 12/ C/cm/sup 2/ electron trap level is required to get high mobility.

Impact of DIBL variability on SRAM static noise margin analyzed by DMA SRAM TEG

The static noise margin (SNM) as well as V<inf>th</inf>, g<inf>m</inf>, body factor, and drain-induced-barrier-lowering (DIBL) in individual transistors in SRAM cells are directly measured by 16k bit device-matrix-array (DMA) SRAM TEG. It is found that, besides V<inf>th</inf> variability, DIBL variability degrades SRAM stability and its V<inf>dd</inf> dependence while the variability of g<inf>m</inf> and body factor has only a small effect.

Sub-50-nm physical gate length CMOS technology and beyond using steep halo

Sub-50-nm CMOS devices are investigated using steep halo and shallow source/drain extensions. By using a high-ramp-rate spike annealing (HRR-SA) process and high-dose halo, 45-nm CMOS devices are fabricated with drive currents of 650 and 300 /spl mu/A//spl mu/m for an off current of less than 10 nA//spl mu/m at 1.2 V with T/sub ox//sup inv/=2.5 nm. For an off current less than 300 nA//spl mu/m, 33-nm pMOSFETs have a high drive current of 400 uA//spl mu/m. Short-channel effect and reverse short-channel effect are suppressed simultaneously by using the HRR-SA process to activate a source/drain extension (SDE) after forming a deep source/drain (S/D). This process sequence is defined as a reverse-order S/D (R-S/D) formation. By using this formation, 24-nm nMOSFETs are achieved with a high drive current of 800 /spl mu/A//spl mu/m for an off current of less than 300 /spl mu/A//spl mu/m at 1.2 V. This high drive current might be a result of a steep halo structure reducing the spreading resistance of source/drain extensions.