Mitsuyoshi Endo

Robust hermetic wafer level thin-film encapsulation technology for stacked MEMS / IC package

This paper reports a thin-film encapsulation technology for wafer level micro-electro-mechanical systems (MEMS) package, using poly-benzo-oxazole (PBO) sacrificial material and plasma enhanced chemical vapor deposited silicon oxide (PECVD SiO) cap layer. This technique, which is applicable for MEMS technologies, saves die size and enables conventional package processes such as dicing, picking, mounting and bonding. Besides the fabrication processes of the thin-film encapsulation, this paper also presents the results of finite element models (FEMs) for the deflection and the mechanical stress of the thin-film caps. Moreover, in order to mount a MEMS chip with the thin- film capsulations and another integrated circuit (IC) chip that controls a MEMS chip in the same package, we have also developed an epoxy reinforcement technique for protecting the thin-film encapsulations and a topography wafer thinning technique for the MEMS chip. And then the system in package (SiP) for the MEMS and IC chips is fabricated successfully based on the mechanical analysis of the SiP process.

In-line wafer level hermetic packages for MEMS variable capacitor

In this paper, we report in-line wafer level hermetic packages (WLP) for MEMS variable capacitors. The beam structure of MEMS vibrates strongly under decompression. Since this vibration causes RF noise, it is necessary to set the pressure around the beam structure at 40000Pa or greater. Therefore, a structure that carries out a resin seal of the hole for etching the cap of a formed in the sacrificial layer process, at atmospheric pressure (101300Pa) is crucial for what. To prevent moisture permeation inside a cap, the resin was coated with a PECVD SiN layer. The developed packages become a hybrid hermetic encapsulation, which consists of PECVD SiN layers. Moreover, the deformation of the cap by external pressure was reduced using a corrugated cap. The developed package is comparatively large (340 times 1100 mum). Nevertheless, after the 265degC reflow test (5 times) and -55degC/125degC thermal cycle test (20 cycles), no cracks were observed in the packages. Since all of such processes and materials are compatible with the CMOS process, this package has very low cost. We present a summary of several aspects of our development activities in this MEMS variable capacitor packaging technology.

Highly reliable and manufacturable in-line wafer-level hermetic packages for RF MEMS variable capacitor

In this paper, we report a thin-film encapsulation technology for wafer-level micro-electro-mechanical systems (MEMS) variable capacitor package. The electrical characteristics of MEMS are adversely affected by moisture. In order to prevent moisture from permeating into a package, the top surface was protected with a plasma-enhanced chemical vapor deposition (PE-CVD) SiN layer. The developed packages become a hybrid thin-film hermetic encapsulation consisting of an internal shell using PE-CVD SiO, a seal layer coating with resin, and an external protective layer formed by PE-CVD SiN. The process is fully compatible with standard low-cost back-end-of-the-line (BEOL) technologies for LSIs as a wafer-level package (WLP). This hybrid structure was very effective for protecting the MEMS device from external moisture. Moreover, the electrode surface area has to be wide, because a wide range of capacities is necessary in MEMS variable capacitors. We have developed a large (1480 × 1080 µm) hermetic thin-film encapsulation as WLP.

Novel wafer-level CSP for stacked MEMS / IC dies with hermetic sealing

Novel wafer-level chip scale package (WL-CSP) applicable to configurations involving stacking of multiple dies has been developed. Since stacked die makes high topography and it is difficult to apply conventional WL-CSP process, gold bonding wires were used for not only connecting stacked dies with one another but also for connecting from each die to CSP terminals. The WL-CSP is also applicable to microelecrromechanical system (MEMS) that requires hermetic sealing. Thin-film encapsulation for MEMS was formed by conventional back end of line (BEOL) process. Followed by die stacking and gold wire forming, chemical vapor deposition (CVD) was applied to make hermetic sealing. The WL-CSP does not require photolithography process on topography wafer. It promises a cost-effective solution for MEMS/IC dies coupled device.