Mj Mart Coenen

In-situ EMC testing using surface current sense wires

In-situ EMC testing is, for large fixed systems and installations within the scope of the European EMC Directive, not a primary requirement other than unintended RF emissions may not affect intended radio frequency communication services, like the requirements of IEC/EN 55011 outside the end-users premises. Whatever happens on the premises of the industrial end-user is a matter of negotiations and agreements between the various system suppliers and the end-user, in particular when EMC is lacking between two or more (sub-) systems installed.

Assembled PCB EMC test methods

Most often, it is unclear where assembled PCBs are going to be used in and how these are being connected and applied. As such, it will be required, both for the OEM manufacturer as well as the end-user/system integrator, to know the EMC properties prior to system integration. EMC is, aside power integrity (PI) and signal integrity (SI), one of the crucial requirements to be met to ensure functional reliability of the end-product. The EMC requirements applicable need to be uncomplicated and easy to verify in a limited amount of test time. Last but not least, these EMC tests have to be applied in an environment which is close to the end-applications foreseen; rack-mounted, stand-alone, etc. The PCB test methods proposed cover the frequency range from (DC) several Hz to several GHz, both on RF emission and immunity. By exchanging the RF disturbance source by an impulse source, the test methods proposed can also be used with impulse immunity tests.

Reducing compliance uncertainty with AMN measurements

In IEC CISPR 16-4-2 [1, 2] tight impedance requirements are given for artificial mains networks (AMN). Unfortunately, these tight requirements will support measurement uncertainty but still not guarantee low compliance uncertainty if the whole test set-up, up to the port of the equipment being tested, is not taken into account. In this paper the impact of the design of the AMN as well as the mains cable used is evaluated. Incorrect cascading of typical AMN elements: impedance stabilizing network, attenuator(s), high-pass filters and impulse limiter results in erroneous findings which affect measurement uncertainty. Introduction of impedance requirements on the mains cable used enhances the compliance uncertainty by 20 dB, which is demonstrated by simulations and measurements.

Dynamic behavior model for SEED analysis; extraction using surface response modelling

System Efficient ESD Design (SEED) requires dynamic behavior models from the devices and circuitry used along the protection chain, typically from the discharge point of entry at the PCB boundary i.e. connector up to the circuits on-chip to be protected. In-between this path there may be external ESD protection i.e. voltage clamping together with parasitic layout effects, interconnect path delay with specific transmission line properties, package design up to on-chip protection design with parasitic layout effects and ultimately the on-chip circuit(s) to be protected, being unpowered or powered.

Low-frequency magnetic-field immunity surface scan method

Many sensor designs incorporating electronics are becoming more vulnerable to low frequency (LF) magnetic field (H-fields) when used in close proximity of electrically driven actuators, linear and rotating motors. The complex geometrical structure of the sensors front-end design is often unknown. The sensors front-end position is where the physical measurement quantity is transferred into an electrical quantity and then led up to the amplification stages. Again, given by the fact that low-frequency H-fields are hard to shield, the externally generated H-fields i.e. magnetic flux penetrates into the few sub-mm square area and induces interfering voltages: U = -dφ/dt = -dB.A/dt. At this moment, no formal H-field immunity requirements nor test methods exist which is applicable in the frequency range 10 Hz to 1 MHz. To be able to characterize the LF H-field immunity of these sensors, a surface scan method has been developed by which local H-fields can be injected in the various orthogonal orientations over the surface of the sensor by which its most sensitive orientation and response can be visualized. Knowing the absolute and orientation sensitivity of sensors can be useful in the selection process of sensors and will determine their fit-for-use prior to system integration.

Time-domain surface scan method

The necessity of using dedicated EMI-receivers and compliant spectrum analyzers with CISPR detectors is based on an outdated approach. The levels that people perceive from AM/FM radio reception and analogue modulated television broadcast signals as interference is taken as reference. In the meanwhile new detectors: C_AV and C_RMS have been defined of which the software algorithm is patented which, as such, is delaying the acceptance of these new detectors to be included in IEC CISPR 16-1-1. For most of the EMC related issues, there is little need for such specific detectors as one has to recalculate the nuisance that the total disturbing signal provokes per system bandwidth anyhow. The effect that an RF disturbance might have on a broadcasted RF signal with limited bandwidth will be completely different from e.g. sensor applications where broadband demodulation might occurs. As such, EMC compliant products may still cause nuisance when other detection criteria apply. Time-domain based EMC measurement systems have been developed with just a single RF input [1]. However, for most of the surface and 3D scanning applications 3 or 4 RF inputs are needed e.g. for measuring the 3 orthogonal E/H-field components and the other input is used for synchronisation. For such applications, modern 4-channel digital oscilloscopes can be used which have add-on mathematical analysis capabilities for the signals obtained. By taking time-domain data with sufficient sampling resolution, the influence onto other susceptible systems can be post-calculated by applying the complex response characteristic of the system being interfered. However efficient data reduction is a prerequisite to limit data storage and enable post-processing.

Noise reduction in nanometre CMOS

With nanometre scaling, the amount of transistors per 100 square millimetre will increase following Moores Law. The maximum power will, without additional cooling, be limited to a few watt whereas the on- and off-chip clock and data speeds will increase further. To accommodate this, the core supply voltages are reduced further down to below 1 volt as where the peripheral supply voltages will have to follow international agreed voltages levels to enable interfacing. While lowering the core supply voltages, the on-chip noise margin will drop accordingly and tight on- and off-chip decoupling measures are necessary. However by application, RF switching noise from nanometre CMOS designs are forced out of their packages through the supply and ground pins when applying conventional off-chip decoupling is applied. In this paper, the state-of-the-art, as well as a new noise reduction technique, which is possible with todays nanometre CMOS processes, will be discussed together with guidance to accompanying complementary off-chip measures.

Discrete spread-spectrum sampling (DSSS) to reduce RF emission and beat frequency issues

Using spread spectrum clocking techniques with digital systems is quite commonly used to reduce RF emission at the higher harmonics, this to fulfill the existing EMC regulations. Results have been reported frequently. However, with analogue interfaces, fixed frequency sampling is still in place for the sake of signal reconstruction and processing algorithms.