Ahm Arthur van Roermund
Eindhoven University of Technology
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Publication
Featured researches published by Ahm Arthur van Roermund.
international solid-state circuits conference | 2013
Pja Pieter Harpe; Eugenio Cantatore; Ahm Arthur van Roermund
Low-power sensor applications e.g. for environmental monitoring, bio-potential recording, and wireless autonomous sensor networks require highly power-efficient ADCs, typically with resolutions of at least 10b. SAR ADCs are generally beneficial in terms of power efficiency. However, the most power-efficient designs currently lack the required accuracy for these applications [1, 2], as they are limited to 9b ENOB. Other designs that have sufficient accuracy (10b) are limited to power efficiencies above 10fJ/conv-step [3]. The aim of this work is to increase the accuracy of highly efficient SAR ADCs beyond 10b, while further improving the efficiency to 2.2fJ/conv-step. To do so, this work introduces a Data-Driven Noise-Reduction method to efficiently suppress comparator noise, applies a segmented capacitive DAC with 250aF unit elements for better efficiency and accuracy, and implements a self-oscillating comparator to locally generate the internally required oversampled clock.
international solid-state circuits conference | 2014
Pja Pieter Harpe; Eugenio Cantatore; Ahm Arthur van Roermund
Autonomous wireless sensor nodes for cloud networks require ultra-low-power electronics. In particular, sensor readout interfaces need low-speed high-precision ADCs for capturing, e.g., bio-potential signals, environmental information, or interactive multimedia. For these applications, state-of-the-art SAR ADCs can provide highly power-efficient solutions (<;10fJ/conversion-step) but with limited accuracy (SNDR <;63dB) [1,2]. Alternatively, ΔΣ ADCs offer higher precision at the cost of lower efficiency (e.g. 84dB SNDR with 54fJ/conversion-step [3]). This work bridges the existing performance gap by extending the accuracy of low-power SAR ADCs to SNDRs in the order of 70-to-80dB. Feedback-controlled data-driven noise reduction [1], oversampling, chopping [4] and dithering [5] techniques are combined to increase both SNR and linearity in a power-efficient way. Various ADC modes are supported by making these techniques individually programmable, thereby extending the application range.
IEEE Journal of Solid-state Circuits | 2013
Pja Pieter Harpe; Eugenio Cantatore; Ahm Arthur van Roermund
This paper presents a power-efficient 10/12 bit 40 kS/s SAR ADC for sensor applications. It supports resolutions of 10 and 12 bit and sample rates from DC up to 40 kS/s to accommodate a variety of sensor applications. A Data-Driven Noise-Reduction method is introduced to selectively enhance the comparator noise performance. In this way, a higher ADC resolution can be achieved with a small increase of the power consumption. A self-oscillating comparator is used to generate the bit-cycling clock internally. In this way, the ADC only requires an external clock at the sample-rate frequency. A segmented capacitive DAC with 250 aF unit elements is applied to save power and to reduce DNL errors at the same time. The implemented prototype in 65 nm CMOS occupies an area of 0.076 mm 2. For the two supported resolutions (10/12 bit), the ADC achieves an ENOB of 9.4 and 10.1 bit while consuming 72 and 97 nW from a 0.6 V supply at 40 kS/s. This leads to power efficiencies of 2.7 and 2.2 fJ/conversion-step for 10 bit and 12 bit resolution, respectively. Furthermore, the leakage power, which is below 0.4 nW, ensures that the efficiency can be maintained down to very low sample rates.
IEEE Transactions on Biomedical Circuits and Systems | 2015
S Shuang Song; Mj Michiel Rooijakkers; Pja Pieter Harpe; C Chiara Rabotti; M Massimo Mischi; Ahm Arthur van Roermund; Eugenio Cantatore
This paper presents a low-voltage current-reuse chopper-stabilized frontend amplifier for fetal ECG monitoring. The proposed amplifier allows for individual tuning of the noise in each measurement channel, minimizing the total power consumption while satisfying all application requirements. The low-voltage current reuse topology exploits power optimization in both the current and the voltage domain, exploiting multiple supply voltages (0.3, 0.6 and 1.2 V). The power management circuitry providing the different supplies is optimized for high efficiency (peak charge-pump efficiency = 90%).The low-voltage amplifier together with its power management circuitry is implemented in a standard 0.18 μm CMOS process and characterized experimentally. The amplifier core achieves both good noise efficiency factor (NEF=1.74) and power efficiency factor (PEF=1.05). Experiments show that the amplifier core can provide a noise level of 0.34 μVrms in a 0.7 to 182 Hz band, consuming 1.17 μW power. The amplifier together with its power management circuitry consumes 1.56 μW, achieving a PEF of 1.41. The amplifier is also validated with adult ECG and pre-recorded fetal ECG measurements.
International Journal of Circuit Theory and Applications | 2000
Ahm Arthur van Roermund; Jaap Hoekstra
This paper describes an overall policy for the design of nanoelectronic systems, showing how specific properties of quantum devices can be exploited instead of being counteracted, by introducing unconventional design approaches. Single-electron tunnelling (SET) circuit ideas, as components for neural networks, are described in more detail. It is argued that the orthodox theory of single-electron devices is not appropriate for circuit design and simulation, and needs reconsideration. An overview of SET circuit designs for neural nodes is given.
international symposium on circuits and systems | 2012
E Elbert Bechthum; Georgi Radulov; J Joseph Briaire; G. Geelen; Ahm Arthur van Roermund
In an RF transmitter, the function of the mixer and the DAC can be combined in a single block: the Mixing-DAC. For the generation of multicarrier GSM signals in a basestation, high dynamic linearity is required, i.e. SFDR>;85dBc, at high output signal frequency, i.e. fout ≈ 4GHz. This represents a challenge which cannot be addressed efficiently by current available hardware or state-of-the-art published solutions. Mixing locality indicates if the mixing operation is executed locally in each DAC unit cell or globally on the combined DAC output signal. The mixing locality is identified as one of the most important aspects of the Mixing-DAC architecture with respect to linearity. Simulations of a current steering Mixing-DAC show that local mixing with a local output cascode can result in the highest linearity, i.e. IMD3<;-88dBc at fout=4GHz.
topical meeting on silicon monolithic integrated circuits in rf systems | 2010
Ejg Erwin Janssen; R Reza Mahmoudi; Edwin van der Heijden; P Pooyan Sakian; Ajm Anton de Graauw; Ralf Pijper; Ahm Arthur van Roermund
This paper presents a two-stage fully integrated 60 GHz differential Low Noise Amplifier implemented in a TSMC bulk CMOS 65 nm technology. Implementation of a voltage-voltage feedback enables the neutralization of the Miller capacitance and the achievement of flat gain with a deviation of ± 0.25 dB over the entire 6 GHz bandwidth. It features a transducer gain (Gt) of 10 dB along with a noise figure (NF) of 3.8 dB, NFmin of 3.7 dB and a constant delay time. IIP3 is 4 dBm. It consumes 35 mW from a 1.2 V supply and only occupies 330 × 170 µm.
topical conference on wireless sensors and sensor networks | 2011
Hao Gao; Pgm Peter Baltus; R Reza Mahmoudi; Ahm Arthur van Roermund
This paper presents the analysis of the performance of charge pump, and the design strategy and efficiency optimization of 2.4GHz micro-power charge pump using 65nm CMOS technology. The model of the charge pump takes account of the threshold voltage variation, bulk modulation, and the major parasitic capacitor. Charge pump is sensitive to the input voltage swing and the actual input voltage swing is less after the capacitor divider, which generates the optimized size transistor. From the mathematic model of the charge pump, the relationship between the charge pump performance and design parameter is presented. After parameter analysis and performance discussion, a design procedure to maximize performance is presented. Corresponding to the design procedure presented in this paper, a high efficiency charge pump at 2.4GHz is presented.
radio frequency integrated circuits symposium | 2016
Hao Gao; K Kuangyuan Ying; M Marion Matters-Kammerer; Pja Pieter Harpe; Q Qian Ma; Ahm Arthur van Roermund; Pgm Peter Baltus
This paper presents a low noise amplifier realized in 40-nm CMOS technology for the 60 GHz ISM band. To reduce the noise contribution from the input passive structure, a new metal slotting method is applied to the transmission line for increasing the effective conducting cross-section area. The design incorporates additional noise matching between the common-source stage and the common-gate stage to reduce the noise impact by the latter stage. The measured noise figure is below 4 dB from 51 GHz to 65 GHz, 3.6 dB at 55 GHz and 3.8 dB at 60 GHz. The achieved 3 dB power gain bandwidth is 13 GHz, from 48 GHz to 61 GHz. The peak transducer gain (Gt) is 15 dB at 55 GHz, and 12.5 dB at 60 GHz. The total power consumption is 20.4 mW.
international symposium on circuits and systems | 2012
Y Yu Lin; Kostas Doris; Ja Hans Hegt; Ahm Arthur van Roermund
This paper presents a dynamic latched comparator suitable for applications with very low supply voltage. It adopts a circuit topology with a separated input stage and two cross-coupled pairs (nMOS and pMOS) stages in parallel instead of stacking them on top of each other as previous works. This circuit topology enables fast operation over a wide input common-mode voltage and supply voltage range. This comparator is designed in 65-nm CMOS technology with standard threshold transistors (VT≈0.4V). Simulation shows that it achieves 5mV sensitivity for a sampling rate of 5GS/s with 1.2V supply voltage, 10mV for 250MS/s with 0.5V supply voltage and 100MS/s with 0.45V supply voltage. The simulated delay time of the proposed comparator is about 30% shorter than the dual-tail dynamic comparator with 0.5V supply voltage and only one third compared to that of the conventional one with 0.6V supply voltage when they are designed to have a similar input referred offset voltage in 65nm CMOS technology.