Mladen Bozanic

Analogue CMOS direct sequence spread spectrum transceiver with carrier recovery employing complex spreading sequences

DSSS (direct sequence spread spectrum) is a form of digital communication where each bit is represented by a unique spreading sequence. DSSS is a promising technique for implementing high speed wireless links. For any DSSS communication system to be successful, an effective, low cost transceiver is required. This paper presents transceiver systems which have the potential to fulfil this role. An analogue DSSS transceiver is presented to demonstrate an ideal receiver and a DDC-CRL (decision directed Costas carrier recovery loop) is presented which performs carrier and phase estimation in the receiver. These systems operate anywhere over a 20 MHz bandwidth within the 2.4 GHz to 2.4835 GHz ISM (industrial, scientific and medical) band and are implemented for the 0.35 mum CMOS process from Austria Microsystems (AMS)

Design methodology for a CMOS based power amplifier deploying a passive inductor

This paper presents the design methodology of an integrated power amplifier (PA), and coins the methodology as a software routine: for a given set of PA specifications, CMOS process parameters, the routine computes the passive component values for a Class-E based PA. The routine includes the matching network for standard impedance loads. The program also provides its user with a spiral inductor calculator, which can be used to determine inductance and parasitic values for an integrated square planar spiral inductor. The same tool has the ability to extract SPICE (tSPICE) netlist of inductor geometry, which can be used in the post-layout simulations of the PA. Operation of the program was demonstrated by simulations in AMS 0.35 mum single-supply process for a 10 dBm, 2.4 GHz PA design.

Design flow for CMOS based Class-E and Class-F power amplifiers

This paper presents the design flow for an integrated power amplifier. The flow is presented as a software routine. For a given set of amplifier specifications and CMOS process parameters, the routine computes the passive component values for a Class-E or Class-F based power amplifier. The routine includes the matching network for standard impedance loads. The routine also provides its user with a spiral inductor search algorithm, which can be used to generate layouts of inductors with Q-factors optimised at a desired frequency. For a typical power amplifier design case where several amplifiers are designed for application over different channels, the routine presented in this paper contributes by streamlining the design flow. The operation of the software routine was demonstrated by simulations in Austriamicrosystems 0.35 µm single-supply process for a 14 dBm, 2.4 GHz power amplifier design.

Cantilever for RF applications: Model and technology

A radio frequency (RF) microelectromechanical systems (MEMS) shunt cantilever is simulated using the Keysight Technologies Advanced Design System up to 65 GHz The electrical and RF performances of the fabricated switch are discussed. The RF simulation results are compared with the measurements for the up and down positions of the implemented MEMS switch.

A 50 GHz SiGe BiCMOS active bandpass filter

This paper presents a second-order active bandpass filter (BPF) at millimeter-wave frequency band using 0.13 µm SiGe BiCMOS technology. A complementary cross-coupled pair based negative resistance technique is applied to compensate for the resistive losses of microstrip line resonators. The proposed active BPF is simulated using the Keysight Technologies (formerly Agilents Electronic Measurement Group) Advanced Design System 2016.01. The center frequency (ƒc), 3-dB bandwidth, and fractional bandwidth of the simulated BPF are 53.85 GHz, 14.18 GHz, and 26.33%, respectively. The BPF shows an insertion loss (IL) of 0.33 dB and a return loss (RL) of 18.03 dB at ƒc. The minimum IL of 0.10 dB and best RL of 26.03 dB are observed in the passband. The noise figure and input 1-dB compression point (P1dB) at ƒc are 7.93 dB and −3.67 dBm, respectively. The power dissipation is 2.62 mW at 1.6 V supply voltage. For the input power level of −10 dBm, the power level of the second harmonic is −46.02 dBc.

Effect of lossy substrates on series impedance parameters of interconnects

The paper presents the effect of lossy silicon (Si) substrates on the frequency-dependent distributed series impedance interconnect parameters - R(ω) and L(ω). The frequency variations of these parameters of the microstrip line for four different conductivities of Si substrate are observed and compared Keysight Technologies Advanced Design System is used for the electromagnetic simulations of the microstrip line structures. Scattering parameters (S-parameters) based equations are used to plot the variations of series impedance parameters as a function offrequency.

Re-inventing postgraduate level teaching and learning in nanoelectronics

In the world where technology changes almost daily, the field of microelectronics or nanoelectronics is becoming an area driving the future. Therefore, more engineers specializing in micro- and/or nanoelectronics are needed in industry internationally. Globally, a distinct shift in nanoelectronic education has already been observed, where postgraduate coursework and part-coursework degrees in microelectronics and nanoelectronics are now being offered alongside the traditional research or coursework degrees in electronics or electrical engineering (light currents). However, in South Africa the situation is lagging; microelectronic or nanoelectronic specializations are offered either as honors degrees or as the research-based studies mentioned, with no dedicated coursework specialization at the masters level. The Faculty of Engineering and the Built Environment of the University of Johannesburg (UJ) has, therefore, diversified the program and qualifications mix because of this need to teach nanoelectronics at the masters level as well, via global part-coursework and a part-research method of delivery. However, approval for a new degree takes a number of years to be completed. Therefore, as an alternative route, nanoelectronic modules with some cross-disciplinary and multi-disciplinary modules are offered as continuing education programs (CEPs) at National Qualification Framework levels 8 and 9. The CEPs bear continuing Engineering Council of South Africa professional development credits, and can be credited as modules in the envisaged masters degrees. The CEPs are delivered via an online approach, which develops student accessibility and brings about flexibility for students who are studying part-time. Enhanced accessibility and the fast-growing level of internet access in Africa will allow the UJ to serve students both regionally and internationally. This paper explores the rationale for the chosen content of the CEPs and ultimately the proposed masters degrees and discusses in detail the online mode of delivery and its benefits, as well as the approach taken to deliver courses according to this model, together with innovative opportunities.

Comparison of Al and Cu interconnects using VHDL-AMS and SPICE modeling

This paper compares the transient characteristics of aluminum (Al) and copper (Cu) microstrip line structures. Interconnects are represented using distributed resistance inductance capacitance (RLC) transmission line (TL) model. The equivalent RLC-ladder networks for Al and Cu interconnects are first implemented using VHDL-AMS, and their time-domain simulation responses are compared. For the verification of the results obtained from VHDL-AMS implementation, the process is repeated with SPICE modeling. Both the simulation results are in good agreement.

Design flow for a SiGe BiCMOS based power amplifier

This paper presents a streamlined design flow for an integrated power amplifier. For a given set of amplifier specifications and BiCMOS process parameters, a software routine computes passive component values for a Class-E or Class-F based power amplifier. The routine includes a matching network for standard impedance loads. Spiral inductor search algorithm is used to generate inductors with Q-factors optimised at a desired frequency. Operation of the software routine is demonstrated by simulations in Austriamicrosystems 0.35 µm single-supply process for the 10 dBm, 2.4 GHz power amplifier design.