Mohamad Hairol Jabbar

3D multiprocessor with 3D NoC architecture based on Tezzaron technology

In this paper, we describe the architecture and implementation of 3D multiprocessor with 3D NoC. The 2 tiers design is based on 16 processors communicating using a 4×2 mesh NoC and will be fabricated using Tezzaron technology with 130 nm Global Foundaries low power standard library. Due to the limitation when investigating NoC performance using simulation, the purpose of this work is to accurately measure NoC performances in real 3D chip when running mobile multimedia applications to evaluate the impact of 3D architecture compared to 2D.

3D IC implementation for MPSOC architectures: Mesh and butterfly based NoC

In the CMOS technologies below 65 nm the wire delay dominates the gate delay. 3D IC design is one solution to deal with this problem. We propose in this work to implement two different MPSOC architectures based on Mesh and Butterfly NoC topologies. We use the 3D IC technology from the Tezzaron Company. Thanks to its symmetry, the mesh based NoC architecture is easier to implement compared to the other one based on the Butterfly NoC. In fact with this one, we have to deal with additional problems like mapping and partitioning. With its long links, the Butterfly architecture is a better example than the mesh topology to prove the efficiency of 3D design.

Smart Recycle Bin: A Conceptual Approach of Smart Waste Management with Integrated Web Based System

Nowadays, the trend is clear that the use of pervasive computing technology has taken place to improve waste management by providing electronic system which utilizing radio frequency identification at bin level. In this paper, we proposed a smart recycle bin application based on information in the smart card to automatically calculate the weight of waste and convert the weight into point then store it into the card. The wastes are tracked by smart bins using a RFID-based system integrating the web-based information system at the host server. Two crucial features of the selective sorting process can be improved using this approach. First, the user is assisted in the application of material waste classification. Second, the smart bin knows its content and can report back to the rest of the recycling chain.

FPGA-in-the-Loop Simulation of Cardiac Excitation Modeling towards Real-Time Simulation

Cardiac excitation is a fundamental mechanism within the heart’s function. One way to understand this mechanism is by using numerical modeling techniques. However, an immense amount of computational time has been required in the simulation that generally involves a large number of parameters. In this paper a simulation study of Luo Rudy Phase I (LR-I) mathematical model by using MATLAB Simulink to solve ordinary differential equations (ODEs) using field programmable gate array (FPGA) towards a real-time simulation of cardiac excitation has been presented. The FPGA could be the best solutions because it is able to provide high performance in solving higher order ODEs for real-time hardware implementation. In fact, the FPGA hardware design can be accelerated by using MATLAB Simulink HDL Coder that automates the hardware description language (HDL) code generation from designed MATLAB Simulink blocks. Furthermore, HDL designed implementation can be verified by using HDL Verifier such as co-simulation and FPGA-in-the-Loop (FIL) approaches to simulate the generated HDL code and verify the results. In this paper, results show that the LR-I cardiac excitation modeling is successfully simulated by the MATLAB Simulink and by using the HDL Coder the designed MATLAB Simulink model is successfully converted into VHDL code and verified through the FIL. These have given a positive outlook towards the FPGA hardware implementation for real-time simulation.

Impact of 3D IC on NoC Topologies: A Wire Delay Consideration

In this paper, we perform an exploration of 3D NoC architectures through physical design implementation based on two tiers Tezzaron 3D technology. The 3D NoC partitioning is done by dividing the NoCs data path component into two blocks placed in the two tiers. Two Stacked NoC architectures namely Stacked 3D-Mesh NoC and Stacked 2D-Hexagonal NoC developed based on this partitioning strategy are analyzed by comparing their performances with Stacked 2D-Mesh NoC and classical 2D-Mesh and 3D-Mesh NoC. In order to measure the impact of wire delay on performance, two technology libraries (130 nm and 45 nm) representing old and advanced technologies have been used for the performance analysis. Results from physical implementations show that in advanced technologies such as 45 nm and below, the performance of Stacked 2D NoC topologies with data path partitioning method have better performances compared with traditional 2D/3D Mesh topologies and Stacked 3D Mesh topology. We advocate here that with stacking there is no need for 3D NoC topologies for advanced 2-tier 3D IC and this is also confirmed for multistage networks like butterfly.

Luo Rudy Phase I excitation modeling towards HDL coder implementation for real-time simulation

This paper presents the simulation study of nonlinear dynamic of cardiac excitation based on Luo Rudy Phase I (LR-I) model towards numerical solutions of ordinary differential equations (ODEs) responsible for cardiac excitation on field programmable gate arrays (FPGAs). As computational modeling needs vast of simulation time, a real-time hardware implementation using FPGA could be the solution as it provides high configurability and performance. For rapid prototyping, MATLAB Simulink that offers a link with the FPGA has been used. Through Simulink HDL Coder, a tool in the MATLAB software that capable to convert the MATLAB Simulink blocks into hardware description language (HDL) code and an FPGA-in-the-loop (FIL) and co-simulation for verification, FPGA hardware implementation can be done. As a result, the LR-I excitation model is successfully simulated by using the MATLAB Simulink and the VHDL code has been successfully generated by the HDL Coder after fixed-point optimization is done. The FIL verification on actual FPGA board also has shown quantitatively comparable results to the MATLAB Simulink simulation. Therefore, the design flow has given a positive outlook in developing this FPGA stand-alone implementation.

FPGA Implementation for Cardiac Excitation-Conduction Simulation Based on FitzHugh-Nagumo Model

The paper examines a method for development of a Field Programmable Gate Array (FPGAs)-based implementation of hardware model for the electrical excitation-conduction in cardiac tissue based on FitzHugh-Nagumo (FHN) mathematical model towards real-time simulation. The FHN model is described by a set of nonlinear Ordinary Differential Equations (ODEs) that includes two dynamic state variables for describing the excitation and the recovery states of a cardiac cell and the model is able to reproduce many characteristics of electrical excitation in cardiac tissues. In this paper, one dimensional (1D) FHN cable model is designed using MATLAB Simulink in order to simulate the conduction of cardiac excitation in coupled nonlinear systems of the heart dynamics. The designed MATLAB Simulink model is then being used for Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) code generation by using HDL Coder that will be implemented on a hardware design FPGA platform of Xilinx Virtex-6 FPGA board. In order to verify and analyze the designed algorithm on the platform, HDL Verifier is used through co-simulation with FPGA-in-the-loop (FIL) simulation and it has shown a significant result which has increased confidence that the algorithm will work in the real FPGA stand-alone application. Therefore, these approaches provide an effective FPGA design flow towards a stand-alone implementation to perform real-time simulations of the cellular excitation-conduction in a large scale cell models.

FPGA-in-the-loop co-simulation of reentrant arrhythmia mechanism in one dimensional (1D) ring-shaped based on FitzHugh-Nagumo model

This paper presents the simulation of reentrant excitation-conduction of cardiac cells realized by coupling 80 active circuits in one dimensional (1D) ring-shaped based on FitzHugh-Nagumo (FHN) model. 1D ring-shaped cable model is designed using Simulink in order to simulate an action potential signal and its conduction for a hardware design by using HDL Coder to automate the model for Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) code generation. Then, the VHDL design is functionally verified on a Field Programmable Gate Array (FPGA) Xilinx Virtex-6 board using HDL Verifier proving the model through FPGA-in-the-Loop (FIL) co-simulation approach. It can then be downloaded into a target FPGA device for real-time simulations. This novel approach of prototyping cardiac reentrant excitation-conduction provides a fast and effective FPGA-based hardware implementation flow towards a stand-alone implementation to perform complex real-time simulations compared with manual HDL designs.

Digitalization of linear back projection algorithm for FPGA implementation

This paper presents the modification of Linear Back Projection (LBP) algorithm for the FPGA implementation purposed. Image reconstruction process is a vital process in tomography system. In order to implement the reconstruction process on FPGA, a slight modification is needed which is digitalize all the floating number of all sensitivity maps matrix data that used in image reconstructed process. As the result of this work, we proposed a new digitalize algorithm that call Digital Linear Back Projection (DLBP) algorithm. The performance of the DLBP compare to original LBP by using MSSIM are 0.9999, 0.9998, 0,9997 and 0.9966 for phantom a, b, c and d respectively.

Optimization in MATLAB for Cardiac Excitation Modeling towards FPGA Standalone Simulation Tools

In past few decades, most of the modern electrophysiological concepts and methods were developed by the computational technique extensively to compute the cardiac action potential in nerve cells. Thus, tissue models consisting of a large number of single cell models cause a problem in the amount of computation required to obtain meaningful results from simulations. One of the solutions to this problem is by implementing the simulation through hardware modeling using a Field Programmable Gate Array (FPGA). Here, a research on developing a real-time simulation tool responsible for reentrant excitations in a ring of cardiac tissue based on the FitzHugh-Nagumo (FHN) model has been carried out by using a Xilinx Virtex-6 XC6VLX240T ML605 development board FPGA. In order to invest some of the time savings for creating the FPGA prototype, rapid prototyping method introduced by MathWorks which are MATLAB Simulink and its HDL Coder toolbox have been used to automate the algorithm design process by converting Simulink blocks into Hardware Description Language (HDL) code for the FPGA using a fixed-point data type in discrete-time framework. In this paper, the method and the optimization of the HDL design through the MATLAB Simulink have been discussed and the FPGA hardware performance in terms of speed, area and power consumption has also been analyzed.