Mohamed A. Elgamel

Interconnect noise analysis and optimization in deep submicron technology

The migration to using ultra deep submicron (UDSM) process, 0.25 /spl mu/m or below, necessitates new design methodologies and EDA tools to address the new design challenges. One of the main challenges is noise. All different types of deep submicron such as cross talk, leakage, supply noise and process variations are obstacles in the way of achieving the desired level of noise immunity without giving up the improvement achieved in performance and energy efficiency. This article describes research directions and various levels of design abstraction to handle the interconnect challenges. These directions include approaches to adopt new analytical methods for interconnects, physical design levels and finally ways to face these challenges early in a higher level of the design process.

Design methodologies for high-performance noise-tolerant XOR-XNOR circuits

Scaling down to deep submicrometer (DSM) technology has made noise a metric of equal importance as compared to power, speed, and area. Smaller feature size, lower supply voltage, and higher frequency are some of the characteristics for DSM circuits that make them more vulnerable to noise. New designs and circuit techniques are required in order to achieve robustness in presence of noise. Novel methodologies for designing energy-efficient noise-tolerant exclusive-OR-exclusive- NOR circuits that can operate at low-supply voltages with good signal integrity and driving capability are proposed. The circuits designed, after applying the proposed methodologies, are characterized and compared with previously published circuits for reliability, speed and energy efficiency. To test the driving capability of the proposed circuits, they are embedded in an existing 5-2 compressor design. The average noise threshold energy (ANTE) is used for quantifying the noise immunity of the proposed circuits. Simulation results show that, compared with the best available circuit in literature, the proposed circuits exhibit better noise-immunity, lower power-delay product (PDP) and good driving capability. All of the proposed circuits prove to be faster and successfully work at all ranges of supply voltage starting from 3.3 V down to 0.6 V. The savings in the PDP range from 94% to 21% for the given supply voltage range respectively and the average improvement in the ANTE is 2.67X.

A Lightweight Collaborative Fault Tolerant Target Localization System for Wireless Sensor Networks

Efficient target localization in wireless sensor networks is a complex and challenging task. Many past assumptions for target localization are not valid for wireless sensor networks. Limited hardware resources, energy conservation, and noise disruption due to wireless channel contention and instrumentation noise pose new constraints on designers nowadays. In this work, a lightweight acoustic target localization system for wireless sensor networks based on time difference of arrival (TDOA) is presented. When an event is detected, each sensor belonging to a group calculates an estimate of the targets location. A fuzzyART data fusion center detects errors and fuses estimates according to a decision tree based on spatial correlation and consensus vote. Moreover, a MAC protocol for wireless sensor networks (EB-MAC) is developed which is tailored for event-based systems that characterizes acoustic target localization systems. The system was implemented on MicaZ motes with TinyOS and a PIC 18F8720 microcontroller board as a coprocessor. Errors were detected and eliminated hence acquiring a fault tolerant operation. Furthermore, EB-MAC provided a reliable communication platform where high channel contention was lowered while maintaining high throughput.

Noise tolerant low voltage XOR-XNOR for fast arithmetic

With scaling down to deep submicron and nanometer technologies, noise immunity is becoming a metric of the same importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequency are the characteristics for deep submicron circuits. This paper proposes a low voltage noise tolerant XOR-XNOR gate with 8 transistors. The proposed gate has been implanted in an already existing (5-2) compressor cell to test its driving capability. The proposed gate is characterized and compared with those published ones for reliability and energy efficiency. The average noise threshold energy (ANTE) and the energy normalized ANTE metrics are used for quantifying the noise immunity and energy efficiency respectively. Results using 0.18m CMOS technology and HSPICE for simulation show that the proposed XOR-XNOR circuit is more noise-immune and displays better power-delay product characteristics than the compared circuit. Also, the circuit proves to be faster in operation and works at all ranges of supply voltage starting from 0.6V to 3.3V.

Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit

Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it were recently added to the draft revision of the IEEE 754 Standard (IEEE P754). In this paper, we present a hardware design for a rounding unit for 64-bit DFP numbers (decimal 64) that use the IEEE P754 binary encoding of DFP numbers, which is widely known as the Binary Integer Decimal (BID) encoding. We summarize the technique used for rounding, present the theory and design of the BID rounding unit, and evaluate its critical path delay, latency, and area for combinational and pipelined designs. Over 86% of the rounding units area is due to a 55-bit by 54-bit binary multiplier, which can be shared with a double-precision binary floating-point multiplier. To our knowledge, this is the first hardware design for rounding IEEE P754 BID-encoded DFP numbers.Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it were recently added to the draft revision of the IEEE 754 Standard (IEEE P754). In this paper, we present a hardware design for a rounding unit for 64-bit DFP numbers (decimal 64) that use the IEEE P754 binary encoding of DFP numbers, which is widely known as the Binary Integer Decimal (BID) encoding. We summarize the technique used for rounding, present the theory and design of the BID rounding unit, and evaluate its critical path delay, latency, and area for combinational and pipelined designs. Over 86% of the rounding units area is due to a 55-bit by 54-bit binary multiplier, which can be shared with a double-precision binary floating-point multiplier. To our knowledge, this is the first hardware design for rounding IEEE P754 BID-encoded DFP numbers.

Novel design methodology for high-performance XOR-XNOR circuit design

As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequency are some of the characteristics for DSM circuits. A novel design methodology for the design of energy-efficient noise-tolerant XOR-XNOR circuits that can operate at low voltages is proposed. The proposed circuits are characterized and compared with previously published circuits for reliability and energy efficiency. To test their driving capability, the proposed gates are implanted in an existing 5-2 compressor design and are shown to provide superior performance. The average noise threshold energy is used for quantifying the noise immunity. Simulation results show that the proposed circuits are more noise-immune and displays better power consumption results as well as power-delay product characteristics. Also, the circuits prove to be faster and successfully work at all ranges of supply voltage starting from 0.6 V to 3.3 V.

A comparative analysis for low power motion estimation VLSI architectures

The power consumption is very critical for portable video applications. The largest portion of power is consumed in the motion estimation module, as it requires a huge amount of computations. This paper compares different full-search motion estimation architectures targeted for low power consumption. Each of the architectures is analyzed, and then compared to the others. An architectural enhancement to further reduce the power consumption is proposed. Our approach is based on further elimination of useless computations without scarifying throughput or optimality. Different benchmarks are used to test and compare the discussed architectures. Analytical and simulation results show the effectiveness of the enhancement.

Noise tolerant low power dynamic TSPCL D flip-flops

The extensive use of a dynamic circuit techniques for higher performance has already been implemented in many circuits like microprocessors. With the scaling down to deep submicron technology and the move towards dynamic circuit techniques, noise immunity is becoming an important metric like power, speed, and area. This paper proposes a technique to achieve low energy consumption in TSPCL D flip-flops. The paper studies some published flip-flops and carries out a modification that reduces the switching activity of some internal nodes, causing a big saving in power consumption. The proposed flip-flop is characterized and compared with those published ones for reliability and energy efficiency. Comparison for speed, power consumption, and noise tolerance is also presented. The average noise threshold energy (ANTE) and the energy normalized ANTE metrics are used for quantifying the noise immunity and energy efficiency, respectively of flip-flops. Results using 0.18 /spl mu/m CMOS technology and HSPICE for simulation, show that the proposed TSPCL D flip-flop achieves reduction in power dissipation ranging from 4.6% to 80% depending on the input pattern and the technology in use. The noise immunization curves show that the modified flip-flop is more susceptible to noise. Hence, one of the known noise immunization techniques should be applied.

Remote Measuring of Flow Meters for Petroleum Engineering and Other Industrial Applications

Reliable remote measuring of flow meters for the petroleum gas industry is proposed in this work. The monitoring of flow rates and the total amount of the fluid flow is collected using a manual process. The main goal of this work is to implement a mechanism that avoids human error and achieves reliable, continuous, and accurate monitoring. We employed the NuFlo Measurement System Model MC-II Flow Analyzer to prototype our monitoring mechanism for measuring the liquid flow and a Crossbow Technology MICA2 mote and MDA300CA Data Acquisition Board to transmit collected data via a wireless sensor network (WSN). The flow analyzer generates a pulse signal whose frequency depends on the flow rate. The mote is used to count the number of pulses and send it to the host computer. An amplifier lets the mote detect the voltage level differences and overcome signal weakness. The host computer stores the data received from the mote into a PostgreSQL database for use in preparing Excel sheets and graphical displays in real time. The flow rate and the total flow amount collected by the host computer match those shown on analyzer. The design and implementation of our prototype serves as a proof of concept of how existing analog sensors used to monitor the flow rate and volume of the oil and water in petroleum production can be integrated with other devices in a WSN.

Crosstalk noise analysis in ultra deep submicrometer technologies

In ultra deep submicron (UDSM) circuit design, the interconnect delay and noise have become the dominant factors in determining circuit performance. Analytical expressions are preferred because simulation is always expensive and ineffective in use with modern designs containing millions of transistors and wires. However, analytical expressions are not sufficiently accurate and do not consider all of interconnect and driver parameters. In this paper, we analyze the effects of all known interconnect and driver parameters on the crosstalk peak noise, crosstalk noise pulse width, and the impact of coupling on aggressor delay. We consider parameters like spacing between wires, wire length, coupling length, load capacitance, rise time of the inputs, place of overlap (near driver or receiver side), frequency, direction of the signals, wire width for both the aggressors and the victim wires. Also, we consider parameters like driver strength as several recent studies considered the simultaneous device and interconnect sizing.