Mohamed Abdelsalam

Evaluation of liver fibrosis and hepatic venous pressure gradient with MR elastography in a novel swine model of cirrhosis

To assess the correlation among MR elastography (MRE) measured liver stiffness (LS), liver fibrosis, and hepatic venous pressure gradient (HVPG) in a swine model of cirrhosis.

Gastroduodenal artery recanalization after transcatheter fibered coil embolization for prevention of hepaticoenteric flow: incidence and predisposing technical factors in 142 patients.

Background Prophylactic occlusion of extrahepatic vessels prior to radioembolization or chemotherapy infusion is an effective method to prevent gastrointestinal complications. Unfortunately, vascular recanalization can occur. Purpose To retrospectively determine the rate and technical factors associated with gastroduodenal artery (GDA) recanalization after transcatheter occlusion with fibered coils. Material and Methods Patients with hepatic malignancy who underwent fibered coil occlusion of the GDA origin for radioembolization or hepatic arterial chemotherapy infusion with at least one subsequent hepatic angiogram between March 2006 and January 2011 were included. One hundred and forty-two patients (men, 71; women, 71) met study criteria. Hepatic arteriograms were reviewed to determine the frequency of arterial recanalization. Additional parameters included: patients’ demographics, GDA diameter, length of coil pack, distance between GDA origin and most cephalad coil, persistent flow at the conclusion of the initial GDA occlusion procedure, platelet count, and international normalized ratio (INR). Chi-square test and pooled t-test were used to compare the two groups. Prospective multivariate analysis was performed with a logistic regression model. Results Twenty-nine of 142 patients (20.4%) experienced GDA recanalization. The distance between the GDA origin and most cephalad coil was significantly greater in the recanalization group than in the non-recanalization group (9.6 mm vs. 12.6 mm, P = 0.01). A prospective multivariate analysis established that the further the coil was from the origin the more likely the GDA was to recanalize. The two groups did not differ on the basis of any other factors examined. Conclusion GDA origin recanalization after fibered coil occlusion is common. The distance between the GDA origin and most cephalad coil appears to be a predisposing factor for recanalization. Familiarity with this phenomenon is beneficial to reduce the likelihood of gastrointestinal tract complications during hepatic locoregional therapy.

A Novel Approach for SVA Generation of DDR Memory Protocols Based on TDML

System Verilog Assertions (SVA) is widely used by hardware designers and verification engineers to apply Assertion Based Verification (ABV) methodology on their hardware designs. However, the ambiguity of design specifications specified by different protocol standards in general and JEDEC memory protocol standards in specific imposes numerous difficulties on designers and verification engineers when translating design specifications into SVA. This motivated us to find a simple way to capture design specifications from JEDEC standard and automatically generate SVA that can be used as checkers for DDR memory protocols. In this paper, we propose a new method to capture design specifications using a timing diagram tool that documents the captured design specifications in a Timing Diagram Mark up Language (TDML) based format and generate SVA from the TDML document. The viability and the potential of our work are demonstrated with an Industrial case study using JEDEC LPDDR3 Memory Protocol Standard.

Minimally invasive image-guided therapies for hepatocellular carcinoma.

Hepatocellular carcinoma (HCC) is the fifth most frequently occurring cancer globally and predominantly develops in the setting of various grades of underlying chronic liver disease, which affects management decisions. Image-guided percutaneous ablative or transarterial therapies have acquired wide acceptance in HCC management as a single treatment modality or combined with other treatment options in patients who are not amenable for surgery. Recently, such treatment modalities have also been used for bridging or downsizing before definitive treatment (ie, surgical resection or liver transplantation). This review focuses on the use of minimally invasive image-guided locoregional therapies for HCC. Additionally, it highlights recent advancements in imaging and catheter technology, embolic materials, chemotherapeutic agents, and delivery techniques; all lead to improved patient outcomes, thereby increasing the interest in these invasive techniques.

SoC verification platforms using HW emulation and co-modeling Testbench technologies

Hardware-assisted verification, or emulation, delivers the capacity and performance for extremely fast, full System-on-Chip (SoC) testing. Emulation enables longer test cases and more tests to be run in less time. In doing so, it allows more design requirements to be covered while more bugs are uncovered. However, emulation is no longer only about performance and capacity. The landscape is shifting beyond these two fundamental benefits in terms of all that can be accomplished virtually with an emulator. As a result, leading electronic-design companies want to take advantage of the benefits of both megahertz verification and a fully virtual, block to SoC level accelerated verification flow. In this paper, we survey different solution methodologies that are built so far and present our SoC verification platform using HW emulation & Co-modeling Testbench technologies. High-performance, high-capacity hardware-assisted emulators and co-modeling Testbench technology can speed up to 10,000x the verification of any System-On-Chip.

A design methodology for system level synthesis of multi-core system architectures

A multi-core system is an integrated circuit containing multiple processor cores that implements most of the functionality of a complex electronic system and some other components like FPGA/ASIC on a single chip. In this paper, we present a novel approach to synthesize multi-core system architectures from Task Precedence Graphs (TPG) models. The front end engine applies efficient algorithm for scheduling and communication contention resolving to obtain the optimal multi-core system architecture in terms of number of processor cores, number of busses, task-to-processor/channel-to-bus mapping, optimal schedule, and HW/SW partition. The back end engine generates a SystemC simulation model using a well-known commercial tool model generation library. The viability and potential of the approach is demonstrated by a case study.

TLM Based Approach for Architecture Exploration of Multicore Systems-on-Chip

Easy, efficient, and automated technique for rapid architectural exploration is achieved using Transaction Level Modeling (TLM) methodology. Architecture evaluation is performed in early stage of the design. An approach for TLM architecture exploration of multi-core systems is presented. Starting with a Task Precedence Graphs (TPG) as a design entry, different architectures with different number of processor cores, number of busses and task-to-processor/channel-to-bus mapping are rapidly explored. The viability and potential of the proposed approach is demonstrated.

Balloon-Assisted Flow Diversion and Selective Catheterization of Target Vessels for Hepatic Transarterial Embolization.

possible that these residents were more likely to complete the survey, introducing response bias, which may have been related to the subject of the email distributed or the title of the electronic survey. Also, a number of residents did not answer all the survey questions, which could contribute to inaccurate results. Another limitation of the study is that the survey respondents were asked to recall their thoughts and intentions from when they were medical students several years earlier. It is certainly possible that the recollections of the senior radiology residents are not entirely accurate. Currently, most medical students are not prepared to make the fellowship and career decision between DR and IR. Most have entered radiology residency considering IR and DR subspecialties and needed resident IR rotations to decide for or against IR as a subspecialty. Most medical students will soon have to decide between IR and DR specialization before participating in IR rotations, which risks applicants making uninformed choices. It is therefore important that medical students are exposed to IR as a career encompassing DR, imageguided procedures, and patient care. Medical school mentors, as well as IR and DR physicians, must improve efforts to educate medical students and create opportunities for extensive exposure to these newly distinct specialties and training programs. DR and IR residency programs should anticipate requests for transfers between these programs within the same institution.

On kernel acceleration of electromagnetic solvers via hardware emulation

We present an emulation-based accelerator for EM simulations in metamaterials.We propose two hardware designs to solve systems of linear equations from the FEM.Both presented designs are run on a physical Veloce 1 emulator from Mentor Graphics.Timing results exceed the performance of several software-based solvers. Display Omitted Finding new techniques to accelerate electromagnetic (EM) simulations has become a necessity nowadays due to its frequent usage in industry. As they are mainly based on domain discretization, EM simulations require solving enormous systems of linear equations simultaneously. Available software-based solutions do not scale well with the increasing number of equations to be solved. As a result, hardware accelerators have been utilized to speed up the process. We introduce using hardware emulation as an efficient solution for EM simulation core solvers. Two different scalable architectures are implemented to accelerate the solver part of an EM simulator based on the Gaussian Elimination and the Jacobi iterative methods. Results show that the performance gap between presented solutions and software-based ones increases as the number of equations increases. For example, solving 2,002,000 equations using our Clustered Jacobi design in single floating-point precision achieved a speed-up of 100.88x and 35.24x over pure software implementations represented by MATLAB and the ALGLIB C++ package, respectively.

On Error Injection for NoC Platforms: A UVM-based Practical Case Study

Error injection has become critically important for testing the reliability of the hardware of any system. Measuring how a design under test reacts to different error injection methodologies is very essential for verification engineers to design dependable Universal Verification Methodology (UVM) scoreboards for error-detection purposes. The main target of this paper is to decide on the feasibility and compatibility of some error injection techniques when used with Networks-on-Chip (NoC) platforms. We target a UVM-based error injection and detection environment with its reusable components. Proposed techniques, introducing both positive and negative test scenarios, are applied to two example NoC components: a base router, which is a simple case study to prove proposed schemes and a configurable router, which is a complex open-source case study that provides the ability of changing the routers architecture with the change of some parameters and applied algorithms. The main novelty of our work is to integrate a full UVM environment with the various approaches of error injection and detection using reusable, generic UVM environment and components for NoC while inspecting network response according to error type and injection methodology.