Magdy A. El-Moursy

Optimum wire sizing of RLC interconnect with repeaters

Repeaters are often used to drive high impedance interconnects. These lines have become highly inductive which can affect signal behavior in long interconnects. The line inductance should, therefore, be considered in determining the optimum number and size of the repeaters driving a line. A tradeoff exists, however, between the transient power dissipation and the minimum propagation delay in sizing long interconnects driven by repeaters. Optimizing the line width to achieve the minimum power delay product, however, can satisfy current high speed, low power design objectives. A reduction in power of 65% and delay of 97% is achieved for an example repeater system.

Exponentially tapered H-tree clock distribution networks

Exponentially tapered interconnect can reduce the dynamic power dissipation of clock distribution networks. A criterion for sizing H-tree clock networks is proposed. The technique reduces the power dissipated by an example clock network by up to 12% while preserving the signal transition times and propagation delays. Furthermore, the inductive behavior of the interconnects is reduced, decreasing the inductive noise. Exponentially tapered interconnects reduce by approximately 20% the difference between the overshoots in the signal at the input of a tree as compared to a uniform tree with the same area overhead.

High throughput architecture for high performance NoC

High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared to the total metal resources required to implement BFT design. The extra power consumption required to achieve the proposed architecture is 3% of the total power consumption of the BFT architecture.

Optimizing Inductive Interconnect for Low Power

The width of an interconnect line affects the total power consumed by a circuit. A trade off exists between the dynamic power and the short-circuit power dissipated in inductive interconnect. The optimum line width that minimizes the total transient power dissipation is determined in this paper. A closed form solution for the optimum width with an error less than 5% is presented. For a specific set of line parameters and resistivities, a reduction in power approaching 78% is achieved as compared to the minimum wire width. Considering the driver size in the design process, the optimum wire and driver size that minimizes the total transient power is also determined.

Inductive interconnect width optimization for low power

The width of an interconnect line affects the total power consumed by a circuit. A tradeoff exists, however, between the dynamic power and the short-circuit power in determining the width of inductive interconnects. The optimum line width that minimizes the total transient power dissipation is determined in this paper. A closed form solution for the optimum width with an error of less than 6% is presented. For a specific set of line parameters and resistivities, the power is reduced by almost 80% as compared to a minimum wire width. Considering the driver size in the design process, the optimum wire and driver size that minimizes the total transient power is also determined.

Shielding effect of on-chip interconnect inductance

Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an RLC load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an RLC load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE.

Wire shaping of RLC interconnects

The optimum wire shape to produce the minimum signal propagation delay across an RLC line is shown to exhibit a general exponential form. The line inductance makes exponential tapering more attractive for RLC lines than for RC lines. For RLC lines, optimum wire tapering achieves a greater reduction in the signal propagation delay as compared to uniform wire sizing. For RLC lines, exponential tapering outperforms uniform repeater insertion. As technology advances, wire tapering becomes more effective than repeater insertion, since a greater reduction in the propagation delay is achieved. Optimum wire tapering achieves a reduction of 36% in the propagation delay in long RLC interconnect as compared to uniform repeater insertion. Wire tapering can reduce both the propagation delay and power dissipation. Optimum tapering for minimum propagation delay reduces the propagation delay by 15% and power dissipation by 16% for an example circuit. The optimum tapering factor to minimize the transient power dissipation of a circuit is described in this paper. An analytic solution to determine the optimum tapering factor that exhibits an error of less than 2% is provided. Wire tapering is also shown to reduce the power dissipation of a circuit by up to 65%. Wire tapering can also improve signal integrity by reducing the inductive noise of the interconnect lines. Wire tapering reduces the effect of impedance mismatch in digital circuits. The difference between the overshoots and undershoots in the signal waveform of an example clock distribution network is decreased by 34% as compared to a uniformly sized network producing the same signal characteristics.

High throughput architecture for CLICHÉ Network on Chip

High Throughput Chip-Level Integration of Communicating Heterogeneous Elements (CLICHÉ) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 40% while preserving the average latency. The area of High Throughput CLICHÉ switch is decreased by 18% as compared to CLICHÉ switch. The total metal resources required to implement High Throughput CLICHÉ design is increased by 7% as compared to the total metal resources required to implement CLICHÉ design. The extra power consumption required to achieve the proposed architecture is 8% of the total power consumption of the CLICHÉ architecture.

Optimum wire shaping of an RLC interconnect

The optimum wire shape for minimum signal propagation delay across an RLC line is shown to have a general exponential form. The line inductance makes exponential tapering more attractive for RLC lines than for RC lines. For RLC lines, optimum wire tapering achieves a higher reduction in the signal propagation delay as compared to uniform wire sizing. Wire tapering can reduce both the propagation delay and power dissipation. A reduction of 15% in the propagation delay and of 16% in the power is achieved for an example circuit.

Traffic-Based Virtual Channel Activation for Low-Power NoC

A large amount of leakage power could be saved by increasing the number of idle virtual channels (VCs) in a network-on-chip (NoC). Low-leakage power switch is proposed to allow saving in power dissipation of the NoC. The proposed NoC switch employs power supply gating to reduce the power dissipation. Two power reduction techniques are exploited to design the proposed switch. Adaptive virtual channel technique is proposed as an efficient technique to reduce the active area using hierarchical multiplexing tree. Moreover, power gating (PG) reduces the average leakage power consumption of proposed switch. The proposed techniques save up to 97% of the switch leakage power. In addition, the dynamic power is reduced by 40%. The traffic-based virtual channel activation (TVA) algorithm is used to determine the traffic status and send adaptation signals to PG units to activate/deactivate the VCs. The TVA algorithm optimally utilizes VCs by deactivating idle VCs to guarantee high-leakage power saving with high throughput. TVA is an efficient and flexible algorithm that defines a set of parameters to be used to achieve minimum degradation in NoC throughput with maximum reduction in leakage power. The whole network average leakage power has been reduced by up to 80% for 2-D-mesh NoC with throughput degradation within only 1%. For 2-D-torus NoC, a saving in power of up to 84% is achieved with <;2% degradation in throughput. The implementation overhead of TVA is negligible.