Yahia Said

Real time hardware co-simulation of Edge Detection for video processing system

A methodology for implementing real-time DSP applications on a field programmable gate arrays (FPGA) using Xilinx System Generator (XSG) for Matlab is presented in this paper. It presents architecture for Edge Detection using Sobel Filter for image processing using Xilinx System Generator. The design was implemented targeting a Spartan3A DSP 3400 device (XC3SD3400A-4FGG676C) then a Virtex 5 (xc5vlx50-1ff676). The Edge Detection method has been verified successfully with no visually perceptual errors in the resulted images.

Embedded real-time video processing system on FPGA

Image Processing algorithms implemented in hardware have emerged as the most viable solution for improving the performance of image processing systems. The introduction of reconfigurable devices and high level hardware programming languages has further accelerated the design of image processing in FPGA. This paper briefly presents the design of Sobel edge detector system on FPGA. The design is developed in System Generator and integrated as a dedicated hardware peripheral to the Microblaze 32 bit soft RISC processor with the EDK embedded system. The input comes from a live video acquired from a CMOS camera and the detected edges are displayed on a DVI display screen.

Human detection based on integral Histograms of Oriented Gradients and SVM

This paper presents a method for human detection in video sequence. The Histogram of Oriented Gradients (HOG) descriptors show experimentally significantly out-performs existing feature sets for human detection. Because of HOG computation influence on performance, we finally choose a more better HOG descriptor to extract human feature from visible spectrum images based on OpenCv and MS VC++. We realized an image descriptor based on Integral Histograms of Oriented Gradients (HOG), associated with a Support Vector Machine (SVM) classifier and evaluate its efficiency.

Real time FPGA acceleration for discrete wavelet transform of the 5/3 filter for JPEG 2000

In the programmable device technologies The continuous advancements enable the widespread use of FPGAs in an increasing number of industrial applications. The availability of powerful software design tools is a fundamental requirement to take advantage of the many advanced and specialized resources included in the latest devices. Video acceleration and processing technologies have become critical for the development of many consumer electronics products. In this paper, we investigate Real Time FPGA implementation of 2-D lifting-based Daubechies 5/3 transforms using a Matlab/Simulink/Xilinx System Generator tool that generates synthesizable VHSIC Hardware Description. This system offers significant advantages: portability, rapid time to market and real time, continuing parametric change in the DWT transform. The proposed model has been designed and simulated using Simulink and System Generator blocks, synthesized with Xilinx Synthesis tool (XST) and implemented on Spartan 3A DSP based XCSD 3400A-4fg476 target device.

Efficient implementation of Sobel edge detection algorithm on CPU, GPU and FPGA

Many applications in image processing have high degrees of inherent parallelism and are thus good candidates for parallel implementation. In fact, programming tools for field programmable gate array FPGA, SIMD instructions on CPU and a large number of cores on graphic processor unit GPU have been developed, but it is still difficult to achieve high performance on these platforms. This paper analyses the distinct features of compute unified device architecture CUDA GPU and summarises the general program mode of CUDA. Furthermore, we present three different implementations of Sobel edge detection on CPU, FPGA and GPU. Tested image data are also used in these hardware platforms to compare computational efficiency of CPU, GPU and FPGA.

High-Level Design for Image Processing on FPGA Using Xilinx AccelDSP

This paper presents the design and implementation of image processing application on field programmable gate array (FPGA). To improve the implementation time, Xilinx AccelDSP, a software for generating hardware description language (HDL) from a high-level MATLAB description has been used. An FPGA-based architecture for Color Space Conversion has been proposed. The design was implemented on Spartan 3A DSP and Virtex 5 devices. Obtained results are discussed and compared with others architectures.

Efficient implementation of sobel filter based on GPUs cards

The Graphics processors or GPUs have become in a few years powerful tools for applications that require a massively parallel computing. Currently include the applications in multimedia processing, the engineering science and image processing in real time. They offer many advantages such as acceleration of treatment and down energy consumption from an equivalent CPU power. In this paper, we will show the effectiveness of our approach sobel filter (features extraction) by parallelizing the processing applied to different images with different sizes.

Cost/performance evaluation for a 3D symmetric NoC router

In this paper, we propose a wormhole router architecture for symmetric 3D-mesh Networks-on-Chip (NoCs) with virtual channels. It uses the credit-based flow control mechanism and dimension-order routing XYZ algorithm. With priority-based scheduling, our 3D on-chip communication model can support the management of different levels of quality-of-service. The router is implemented on FPGA device using the Xilinx ISE software. Various designs were synthesized to verify the capability of our router. From the implementation results, the proposed router architecture enables a higher data rate and low latency at a reasonable power and area overheads. Furthermore, we demonstrate an analysis and comparison of the cost and performance results between the 2D and 3D designs.

Pedestrian detection using covariance features

Detecting pedestrians is a challenging problem owing to the motion of the subjects, the camera and the background and to variations in pose, appearance, clothing, illumination and background clutter. The Region Covariance Matrix (RCM) descriptors show experimentally significantly out-performs existing feature sets for pedestrian detection. In this paper, we present an efficient features extraction scheme: the Integral CovReg, inspired from Region Covariance Matrix (RCM) descriptors, combined with SVM classifier for pedestrian detection.