Mohamed El-Nozahi

High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique

A low drop-out (LDO) regulator with a feed-forward ripple cancellation (FFRC) technique is proposed in this paper. The FFRC-LDO achieves a high power-supply rejection (PSR) over a wide frequency range. Complete analysis and design steps of the FFRC-LDO are presented in this paper. Kelvin connection is also used to increase the gain-bandwidth of the LDO allowing for faster transient performance. The LDO is implemented in 0.13 ?m CMOS technology and achieves a PSR better than - 56 dB up to 10 MHz for load currents up to 25 mA. Load regulation of 1.2 mV for a 25 mA step is measured, and the whole LDO consumes a quiescent current of 50 ?A with a bandgap reference circuit included. To our knowledge, this is the first LDO that achieves such a high PSR up to 10 MHz.

A CMOS Low-Noise Amplifier With Reconfigurable Input Matching Network

A reconfigurable low-noise amplifier (LNA) with tunable input matching network is proposed. The tunable input matching network provides continuous tuning of the input resonant circuit. The LNA is implemented using 0.13-mum CMOS technology. The amplifier has a tuning range of 1.9-2.4 GHz with an input return loss better than -13 dB. The LNA has a measured voltage gain of 10-14 dB and a noise figure of 3.2-3.7 dB within the band. The LNA consumes 14 mA from a 1.2-V supply. The detailed analysis of the proposed LNA, including the tuning range and additional noise of the proposed reconfigurable input matching network, is presented. To our knowledge, this is the first architecture that provides continuous tuning of the input matching network.

An Inductor-Less Noise-Cancelling Broadband Low Noise Amplifier With Composite Transistor Pair in 90 nm CMOS Technology

A new broadband low-noise amplifier (LNA) is proposed in this paper. The LNA utilizes a composite NMOS/PMOS cross-coupled transistor pair to increase the amplification while reducing the noise figure. The introduced approach provides partial cancellation of noise generated by the input transistors, hence, lowering the overall noise figure. Theory, simulation and measurement results are shown in the paper. An implemented prototype using IBM 90 nm CMOS technology is evaluated using on-wafer probing and packaging. Measurements show a conversion gain of 21 dB across 2-2300 MHz frequency range, an IIP3 of -1.5 dBm at 100 MHz, and minimum and maximum noise figure of 1.4 dB and 1.7 dB from 100 MHz to 2.3 GHz for the on-wafer prototype. The LNA consumes 18 mW from 1.8 V supply and occupies an area of 0.06 mm2.

A 25mA 0.13µm CMOS LDO regulator with power-supply rejection better than −56dB up to 10MHz using a feedforward ripple-cancellation technique

Low drop-out (LDO) linear regulators have become a key building block in portable communication systems for power management ICs. The LDO usually comes after a switching DC-DC converter to reduce the output ripples and provide a regulated voltage source for noise-sensitive blocks. For a higher level of integration, there is a need to increase the operating frequency of the switching converters [1]. This necessitates a subsequent LDO regulator with high ripple rejection at frequencies up to several MHz. These LDO regulators should also provide a low drop-out voltage to cope with the low supply voltage of the state-of-the-art CMOS technologies. In addition, due to the feedback nature of the system, the LDO should be stable for a wide range of supply currents while consuming a very low quiescent current.

Low Drop-Out Voltage Regulators: Capacitor-less Architecture Comparison

Demand for system-on-chip solutions has increased the interest in low drop-out (LDO) voltage regulators which do not require a bulky off-chip capacitor to achieve stability, also called capacitor-less LDO (CL-LDO) regulators. Several architectures have been proposed; however comparing these reported architectures proves difficult, as each has a distinct process technology and specifications. This paper compares CL-LDOs in a unified matter. We designed, fabricated, and tested five illustrative CL-LDO regulator topologies under common design conditions using 0.6?m CMOS technology. We compare the architectures in terms of (1) line/load regulation, (2) power supply rejection, (3) line/load transient, (4) total on-chip compensation capacitance, (5) noise, and (6) quiescent power consumption. Insights on what optimal topology to choose to meet particular LDO specifications are provided.

A Millimeter-Wave (23–32 GHz) Wideband BiCMOS Low-Noise Amplifier

This paper presents a 23-32 GHz wideband BiCMOS low-noise amplifier (LNA). The LNA utilizes coupled-resonators to provide a wideband load. To our knowledge, the proposed LNA achieves the widest bandwidth with minimum power consumption using 0.18 ¿m BiCMOS technology in K-band. Analytical expressions for the wideband input matching, gain, noise figure and linearity are presented. The LNA is implemented using 0.18 ¿m BiCMOS technology and occupies an area of 0.25 mm2 . It achieves a voltage gain of 12 dB, 3-dB bandwidth of 9 GHz, noise figure between 4.5-6.3 dB, linearity higher than -6.4 dBm with a power consumption of 13 mW from a 1.5 V supply.

A 20–32-GHz Wideband Mixer With 12-GHz IF bandwidth in 0.18-

This paper presents a 20-32-GHz wideband BiCMOS mixer with an IF bandwidth of 12 GHz. The mixer utilizes an inductive peaking technique to extend the bandwidth of the downconverted IF signal. To our knowledge, the proposed mixer achieves the widest IF bandwidth using silicon-based technologies in K-band. Analytical expressions for the conversion gain and output noise of the proposed mixer are presented. The wideband mixer is implemented using 0.18-μm BiCMOS technology and occupies an area of 0.19 mm2. It achieves a conversion gain of 3 dB, a noise figure between 10.5 and 13.0 dB, and an IIP3 higher than 0.5 dBm with a power consumption of 18 mW from a 1.8-V supply.

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A systematic system-level design methodology for multiband-multistandard (MB-MS) wideband/reconfigurable CMOS receivers is presented. The methodology determines the specifications (noise figure (NF) and linearity) for each building block to minimize the overall power consumption. System-level simulations show that the gain variation of the LNA for various bands/standards is an important factor in minimizing the power consumption for any MB-MS receiver. Analytical expressions for the optimum gain variation of the LNA, NF, and input-referred third-order intercept point of each building block are presented. The design methodology is applied to a wideband receiver covering Global Systems for Mobile Communications (GSM) 900- and 1900-MHz bands, Global Positioning Systems (GPS), and wideband code-division multiple-access (WCDMA) standards. As an example, the estimated power consumption is reduced by 40% when compared with the approach where the gain of the LNA is constant.

SiGe Process

This paper examines different designs for tunable bandpass sigma delta modulators. Both discrete and continuous time implementations are considered. Comparison between different tuning methods is demonstrated using MATLAB simulations. Results show that discrete time modulators using variable coefficients are best suited for tunability

Power-Aware Multiband–Multistandard CMOS Receiver System-Level Budgeting

A new wideband low noise amplifier (LNA) is proposed in this paper. The LNA utilizes a composite NMOS/PMOS cross-coupled transistor pair to increase the amplification while reducing the noise figure. The introduced approach provides partial cancellation of noise generated by the input transistors, hence, lowering the overall noise figure. An implemented prototype using IBM 90 nm CMOS technology shows a measured conversion gain of 20 dB across 2-1100 MHz frequency range, an IIP3 of -1.5 dBm at 100 MHz, and minimum and maximum noise figure of 1.43 dB and 1.9 dB from 100 MHz to 1.1 GHz. The LNA consumes 18 mW from 1.8 V supply and occupies an area of 0.06 mm2.