Mohamed Salah Azzaz

Design and FPGA implementation of a wireless hyperchaotic communication system for secure real-time image transmission

In this paper, we propose and demonstrate experimentally a new wireless digital encryption hyperchaotic communication system based on radio frequency (RF) communication protocols for secure real-time data or image transmission. A reconfigurable hardware architecture is developed to ensure the interconnection between two field programmable gate array development platforms through XBee RF modules. To ensure the synchronization and encryption of data between the transmitter and the receiver, a feedback masking hyperchaotic synchronization technique based on a dynamic feedback modulation has been implemented to digitally synchronize the encrypter hyperchaotic systems. The obtained experimental results show the relevance of the idea of combining XBee (Zigbee or Wireless Fidelity) protocol, known for its high noise immunity, to secure hyperchaotic communications. In fact, we have recovered the information data or image correctly after real-time encrypted data or image transmission tests at a maximum distance (indoor range) of more than 30 m and with maximum digital modulation rate of 625,000 baud allowing a wireless encrypted video transmission rate of 25 images per second with a spatial resolution of 128 × 128 pixels. The obtained performance of the communication system is suitable for secure data or image transmissions in wireless sensor networks.

Real-time FPGA implementation of Lorenz's chaotic generator for ciphering telecommunications

In this paper, we present a new approach for realtime FPGA implementation of the random key based Lorenzs chaotic generator for data stream encryption. We propose a structural hardware architecture designed for a small chip area and high speed performance. This architecture is particularly attractive since it provides a low-cost security telecommunication solution while holding or increasing the encryption throughput rate. We show its feasibility through implementation which is detailed and presented using Virtex Xilinx FPGA. This architecture employs only 1926 slices and allows achieving a random key throughput rate of 124 Mbps by using a low system clock with a frequency of up to 15,5 MHz allowing low power consumption especially for embedded applications.

Robust chaotic key stream generator for real-time images encryption

In this paper, we propose a robust and compact design architecture of hardware chaotic key generator for real-time images encryption. The new proposed approach combines the perturbation technique with a non-linear switching between multiple three-dimensional continuous chaotic systems. The originality of this new scheme is that it allows a low-cost image encryption for embedded systems while still providing a good trade-off between performance and hardware resources. This pipelined architecture is particularly attractive since it provides a high security. Numerical simulations and real-time experimental results using Xilinx FPGA Virtex technology have demonstrated the feasibility and the efficiency of our secure solution and can be applied to many secure real-time embedded applications in System on Chip (SoC). Thorough experimental tests are carried out with detailed analysis, demonstrating the high security and fast encryption speed of the new scheme while still able to resist statistical and key analysis attacks.

Real-time image encryption based chaotic synchronized embedded cryptosystems

This paper proposes a new and efficient way to deal with the chaotic synchronization for embedded hardware cryptosystems and its FPGA implementation for designing a real time image secure symmetric encryption scheme. The implementation and experimental results mapped on two Xilinx FPGA Virtex technology platforms demonstrate the feasibility and the usefulness of our secure solution. The originality of this new scheme is that it allows a low cost image encryption for embedded systems while still providing a good trade-off between performance and hardware resources. Thorough experimental tests are carried out with detailed analysis, demonstrating the high security and fast encryption speed of the new scheme while still able to resist statistical analysis attack.

First Experimental Solution for Channel Noise Sensibility in Digital Chaotic Communications

An interesting and original solution to the high channel noise sensibility problem of digital chaotic communications is proposed. The solution idea consist of avoiding disruption of the slave/receiver dynamics by injecting the driving signal. To realize experimentally this pertinent idea, an FPGA-based hardware architecture is developed, flrstly to trigger the generation of the slave/receiver chaotic dynamics at each received data detection, and secondly to synchronize the driving signal with the slave generated chaotic signal for the demodulation operation. We have tested and validated the proposed solution through experimental realization of a wireless hyperchaotic communication system based on ZigBee communication protocol. Real-time results of experimental wireless communication tests are presented. The obtained results show the efiectiveness and the robustness of the proposed solution against real channel noise in digital chaotic

New hardware Cryptosystem based chaos for the secure real-time of embedded applications

This paper proposes a new Cryptosystem for encryption of the real-time embedded applications. The proposed hardware architecture is based on a chaotic rule switching of several three-dimensional continuous chaotic data generators. The originality of the proposed approach is a new stream chaotic key generator used for real time data encrypt and decrypt. Our architecture, implemented in Virtex Xilinx FPGA technology, is particularly attractive since it provides a very low-cost security solution while holding or increasing the throughput rate encryption. Moreover, the application and experimental results for speech encrypted signal effectively hides the original speech signal after synchronization between the transmitter and the receiver which decrypted recovers the original speech signal with reasonable inteligibility.

Real time hardware implementation of a new Duffing's chaotic attractor

This paper proposes a new approach for real time FPGA implementation of a new chaotic generator characterized by a new three-scroll chaotic attractor. The originality of this chaotic generator is that is obtained with some bifurcation parameters of Duffings chaotic oscillator. Our new chaotic attractor shows the richness chaotic behavior of the Duffings oscillator. In addition, its hardware implementation using Virtex Xilinx FPGA technology is particularly attractive since it provides good performances in terms of throughput and resources cost required. This particularity allows lowing power consumption especially for embedded applications.

A new image crypto-compression system SPIHT-PSCS

In this paper, a new algorithm combined compression and image encryption is presented. The proposed algorithm can be used in the field of high-speed confidential data transmission where security is required. The compression is based on a hierarchical structure called SPIHT(Set Partitioning in Hierarchical Trees). This compression is followed by an encryption scheme PSCS (Parametric Switching Chaotic System). The performances of this technique were evaluated in terms of compression quality and data security. Simulation results have shown the effectiveness of this technique, and thereafter, it is ready for a hardware implementation.

Real-time FPGA implementation of Lü's chaotic generator for cipher embedded systems

In this paper, a new approach to real-time FPGA implementation of chaotic generator of the random key based Lüs chaotic generator for data stream encryption is presented. We propose a structural hardware architecture designed for a small chip area and high speed performance. This architecture is particularly attractive since it provides a low-cost security telecommunication solution while holding or increasing the encryption throughput rate. We show its feasibility through implementation which is detailed and discussed using Virtex Xilinx FPGA. This architecture employs only 1115 slices and allows achieving a random key throughput rate of 182.9 Mbps by using a low system clock with a frequency of up to 22.868 MHz allowing low power consumption especially for embedded applications.

Hardware Design of Embedded Systems for Security Applications

Embedded systems are electronic computer systems designed for dedicated operating functions, often while respecting several constraints like real-time computing, power consumption, size and cost, etc. Embedded systems control many devices in common use today such as smartphones, GPS, codec GSM, decoders, MP3, MPEG62, MPEG4, PDAs, RFIDs, smart cards and networked sensors etc. Generally, they are controlled by one or more main processing cores that are typically either Microcontrollers, Digital Signal Processors (DSPs) or Field Programmable Gate Arrays (FPGAs). These systems are embedded as part of a complete electronic system, often including software, hardware, and communication and sensor parts. By contrast, a general-purpose computer such as a Personal Computer (PC) is designed to be flexible and to meet a wide range of end-user needs. The key characteristic of an embedded system is that it is dedicated to the handling of a particular task. They may require very powerful processors and extensive communications. Ideally, these embedded systems are completely self-contained and will typically run off a battery source for many years before the batteries need to be changed or charged. Since such systems are embedded and dedicated to specific tasks, design engineers search to optimise them by reducing their size (miniaturisation made possible by advanced IC design in order to couple full communication subsystems to sophisticated sensors) and cost in terms of energy consumption, memory and logic resources, while increasing their reliability and performance. Consequently, embedded systems are especially suited for use in transportation, medical applications, safety and security. Indeed, in dealing with security, embedded systems can be self-sufficient and should be able to deal with communication systems. Considering these specific conditions, in the fields of information and communication technology, embedded systems designers are faced with many challenges in terms of both the trade-off between cost/performance/power and architecture design. This is especially true for embedded systems designs, which often operate in non-secure environments, while at the same time being constrained by such factors as computational capacity, memory size and in particular power consumption. One challenge is in the design of hardware architecture able to meet the appropriate level of security and – consequently – the best trade-off between hardware resources and the best throughput rates for real-time embedded applications.