Camel Tanougast

A new deadlock-free fault-tolerant routing algorithm for NoC interconnections

In this paper, we present a new deadlock-free fault-tolerant adaptive routing algorithm for the 2D mesh NoC interconnections. The main contribution of this routing algorithm is that it allows both, routing of messages in the networks incorporating the regions not necessarily rectangular, and routing to all nodes which are not completely blocked by faulty nodes. The proposed routing algorithm is based on a modified turn model and well known XY algorithm. We detail the basic principle of this routing algorithm, prove its deadlock freeness, its feasibility and efficiency through the simulation results.

CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs

The growing complexity of integrated circuits imposes to the designers to change and direct the traditional bus-based design concepts towards NoC-based. Networks on-chip (NoCs) are emerging as a viable solution to the existing interconnection architectures which are especially characterized by high level of parallelism, high performances and scalability. The already proposed NoC architectures in the literature are destined to System-on-chip (SoCs) designs. For a FPGA-based system, in order to take all benefits from this technology, the proposed NoCs are not suitable. In this paper, we present a new paradigm called CuNoC for intercommunication between modules dynamically placed on a chip for the FPGA-based reconfigurable devices. The CuNoC is based on a scalable communication unit characterized by unique architecture, arbitration policy base on the priority-to-the-right rule and modified XY adaptive routing algorithm. The CuNoC is namely adapted and suited to the FPGA-based reconfigurable devices but it can be also adapted with small modifications to all other systems which need an efficient communication medium. We present the basic concept of this communication approach, its main advantages and drawbacks with regards to the other main already proposed NoC approaches and we prove its feasibility on examples through the simulations. Performance evaluation and implementation results are also given.

CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs

In this article, we present CuNoC, a new paradigm for intercommunication between modules dynamically placed on a chip for FPGA-based reconfigurable devices. The CuNoC is based on scalable communication unit called CU which allows the simultaneous communication between several processing elements placed on the chip. We present the basic concept of this communication approach, its main advantages and drawbacks with regards to the other main NoC approaches already proposed.

Design and FPGA implementation of a wireless hyperchaotic communication system for secure real-time image transmission

In this paper, we propose and demonstrate experimentally a new wireless digital encryption hyperchaotic communication system based on radio frequency (RF) communication protocols for secure real-time data or image transmission. A reconfigurable hardware architecture is developed to ensure the interconnection between two field programmable gate array development platforms through XBee RF modules. To ensure the synchronization and encryption of data between the transmitter and the receiver, a feedback masking hyperchaotic synchronization technique based on a dynamic feedback modulation has been implemented to digitally synchronize the encrypter hyperchaotic systems. The obtained experimental results show the relevance of the idea of combining XBee (Zigbee or Wireless Fidelity) protocol, known for its high noise immunity, to secure hyperchaotic communications. In fact, we have recovered the information data or image correctly after real-time encrypted data or image transmission tests at a maximum distance (indoor range) of more than 30 m and with maximum digital modulation rate of 625,000 baud allowing a wireless encrypted video transmission rate of 25 images per second with a spatial resolution of 128 × 128 pixels. The obtained performance of the communication system is suitable for secure data or image transmissions in wireless sensor networks.

Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system

Abstract In this paper we present a new temporal partitioning methodology used for the data-path part of an algorithm for the reconfigurable embedded system design. This temporal partitioning uses an assessing trade-offs in time constraint, design size and field programmable gate arrays device parameters (circuit speed, reconfiguration time). The originality of our method is that we use the dynamic reconfiguration in order to minimize the number of cells needed to implement the data-path of an application under a time constraint. Our method consists, by taking into account the used technology, in evaluating the algorithm area and operators execution time from data flow graph. Thus, we deduce the right number of reconfigurations and the algorithm partitioning for Run-Time Reconfiguration implementation. This method allows avoiding an oversizing of implementation resources needed. This optimizing approach can be useful for the design of an embedded device or system. Our approach is illustrated by various reconfigurable implementations of real time image processing data-path.

A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems

In this paper, we propose a hardware preemptive multitasking mechanism which uses scan-path register structure and allows identifying the total tasks register size for the FPGA-based reconfigurable systems. The main objective of this preemptive mechanism is to suspend hardware task having low priority, replace it by high-priority task and restart them at another time (and/or from another area of the FPGA in FPGA-based designs). The main advantages of the proposed method are that it provides an attractive way for context saving and restoring of a hardware task without freezing other tasks during pre-emption phases and a small area overhead. We show its feasibility by allowing us to design a simple computing example as well as the implementation of AES-128 encryption algorithm which are presented in and detailed on the Xilinx Virtex FPGA technology.

Smart Reliable Network-on-Chip

In this paper, we present a new network-on-chip (NoC) that handles accurate localizations of the faulty parts of the NoC. The proposed NoC is based on new error detection mechanisms suitable for dynamic NoCs, where the number and position of processor elements or faulty blocks vary during runtime. Indeed, we propose online detection of data packet and adaptive routing algorithm errors. Both presented mechanisms are able to distinguish permanent and transient errors and localize accurately the position of the faulty blocks (data bus, input port, output port) in the NoC routers, while preserving the throughput, the network load, and the data packet latency. We provide localization capacity analysis of the presented mechanisms, NoC performance evaluations, and field-programmable gate array synthesis.

A scalable and embedded FPGA architecture for efficient computation of grey level co-occurrence matrices and Haralick textures features

This paper presents a novel and optimized embedded architecture based FPGA for an efficient and fast computation of grey level co-occurrence matrices (GLCM) and Haralick textures features for use in high throughput image analysis applications where time performance is critical. The originality of this architecture allows for a scalable and a totally embedded on Chip FPGA for the processing of large images. The architecture was implemented on Xilinx Virtex-FPGAs without the use of external memory and/or host machine. The implementations demonstrate that our proposed architecture can deliver a high reduction of the memory and FPGA logic requirements when compared with the state of the art counterparts and it also achieves much improved processing times when compared against optimized software implementation running on a conventional general purpose processor.

A new high-performance scalable dynamic interconnection for FPGA-based reconfigurable systems

Networks on chip (NoCs) present viable interconnection architectures which are especially characterized by high level of parallelism, high performances and scalability. The already proposed NoC architectures in literature are mostly destined to system-on-chip (SoCs) designs. For a FPGA-based reconfigurable system, the proposed NoCs are not suitable. In this paper, we present a new high-performance interconnection approach destined for FPGA-based reconfigurable system. Our proposed NoC is based on a scalable communication unit characterized by its particularly architecture, an arbitration policy based on the priority-to-the-right rule and high performances. We present the basic concept of this communication approach and we prove its feasibility on examples through the simulations. Implementation results are also detailed.

Real-time FPGA implementation of Lorenz's chaotic generator for ciphering telecommunications

In this paper, we present a new approach for realtime FPGA implementation of the random key based Lorenzs chaotic generator for data stream encryption. We propose a structural hardware architecture designed for a small chip area and high speed performance. This architecture is particularly attractive since it provides a low-cost security telecommunication solution while holding or increasing the encryption throughput rate. We show its feasibility through implementation which is detailed and presented using Virtex Xilinx FPGA. This architecture employs only 1926 slices and allows achieving a random key throughput rate of 124 Mbps by using a low system clock with a frequency of up to 15,5 MHz allowing low power consumption especially for embedded applications.