Mohammad Hossein Neishaburi

Reliability aware NoC router architecture using input channel buffer sharing

To address the increasing demand for reliability in on-chip networks, we proposed a novel Reliability Aware Virtual channel (RAVC) NoC router micro-architecture that enables both dynamic virtual channel allocations and the rational sharing among the buffers of different input channels. In particular, in the case of failure in routers, the virtual channels of routers surrounding the faulty routers can be totally recaptured and reassigned to other input ports. Moreover, our proposed RAVC router isolates the faulty router from occupying network bandwidth. Experimental result shows that proposed micro-architecture provides 7.1% and 3.1 % average latency decrease under uniform and transpose traffic pattern. Considering the existence of failures in routers of on-chip network, RAVC provides 28% and 16% decrease in the average packet latency under the uniform and transpose traffic pattern respectively.

ERAVC: Enhanced reliability aware NoC router

The continuing advances in processing technology result in significant decreases in the feature size of integrated circuits. This shrinking leads to increases in susceptibility to transient errors and permanent faults. Network on Chips (NoCs) are poised to address the demands for high bandwidth communication among processing elements. The structural redundancy inherited in NoC-based design can be exploited to improve reliability and compensate for the effects of failures in digital systems. In this paper, we propose an enhanced fault tolerant micro-architecture for NoC routers. The proposed router supplies dynamic virtual channel allocation using Unified Buffer Structure (UBS) and History Aware Free-slot Tracker (HAFT). Plus, to reduce the associated performance costs of retransmissions in the case of failure, the proposed router employs a high-performance fault tolerant control flow, handling both transient and permanent faults without extra retransmission buffer requirements. Experimental results show a significant improvement in reliability as well as decreases in the average latency and energy consumption.

An efficent dynamic multicast routing protocol for distributing traffic in NOCs

Nowadays, in MPSoCs and NoCs, multicast protocol is significantly used for many parallel applications such as cache coherency in distributed shared-memory architectures, clock synchronization, replication, or barrier synchronization. Among several multicast schemes proposed in on chip interconnection networks, path-based multicast scheme has been proven to be more efficient than the tree-based, and unicast-based. In this paper a low distance path-based multicast scheme is proposed. The proposed method takes advantage of the network partitioning, and utilizing of an efficient destination ordering algorithm. The results in performance, and power consumption show that the proposed method outstands the previous on chip path-based multicasting algorithms.

Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections

The routing algorithm benefits from congestion-aware flow control, making better routing decisions. The proposed routing algorithm is architected to fully exploit congestion-aware flow controls which come from neighboring switches and versatile reuse of available resources for concurrent input and output selections to remedy unbalance energy distribution due to peak-power and congested area. We simulate and evaluate the proposed architecture in term of network latency, hardware overhead and energy consumption. Our results show for effectiveness of the proposed technique in balancing the performance and energy of NoC designs

Enabling efficient post-silicon debug by clustering of hardware-assertions

Bug-free first silicon is not guaranteed by the existing pre-silicon verification techniques. To have impeccable products, it is now required to identify any bug as soon as the first silicon becomes available. We consider the Assertion Based Verification techniques for the post-silicon debugging based on the insertion of hardware checkers in the debug infrastructure for complex systems on chip. This paper proposes a method to cluster hardware-assertion checkers using the graph partitioning approach. It turns out that having the clusters of hardware-assertions and controlling each cluster selectively during the debug mode and normal operation of the circuit makes integration of assertions inside the circuits easier, and causes lower energy consumption and efficient debug scheduling.

Hierarchical trigger generation for post-silicon debugging

The post-silicon debugging process is aimed at locating design errors and electrical errors that concealed themselves during the whole process of pre-silicon verification. Although during post-silicon validation engineers can exploit the high speed of hardware prototype to exercise huge amount of test vectors, low level of real-time observability and controllability of signals inside the prototype is too big an issue for them. Various DFD techniques have come to improve observability of signals and expedite root cause analysis. Recently, typical practical DFD approaches are based on the Embedded Logic Analysis ELA. Since ELA has limitation in terms of the amount of data that can acquire in a debug experiment, we have to either increase the size of trace buffer or try to use trigger unit that can effectively control when to acquire the debug data. In this paper, we propose ZiMH a trigger generator that builds trigger unit. Additionally, it provides resourceful trace information for root cause analysis. Major advantages of generated trigger unit over traditional trigger units are: 1) it facilitates failure localization and root-cause analysis by keeping the trace of interaction that leads to the failure 2) it can be tuned for specific location to avoid the huge cost related to interfacing with trace signals 3) it can get parameterized to generate several trigger units that can be placed inside the limited area.

NISHA: A fault-tolerant NoC router enabling deadlock-free Interconnection of Subnets in Hierarchical Architectures

Decrease in the Integrated Circuit (IC) feature sizes leads to the increase in the susceptibility to transient and permanent errors. The growing rate of such errors in ICs intensifies the need for a wide range of solutions addressing reliability at various levels of abstractions. Network on Chip (NoC) architecture has been introduced to address the increasing demand for communication bandwidth among processing cores. The structural redundancy inherited in NoC-based system can be leveraged to improve reliability and compensate for the effects of failures. In this paper, we propose a fault-tolerant NoC router NISHA, which stands for No-deadlock Interconnection of Subnets in Hierarchical Architectures. Armed with a new flow control mechanism, as well as an enhanced Virtual Channel (VC) regulator, the proposed router can mitigate the effects of both transient and permanent errors. A Dynamic/Static virtual channel allocation with respect to the local and global traffic is supported in NISHA; thereby, it maintains a deadlock-free state in the presence of routers or link failures in hierarchical topologies. Experimental results show an enhanced operation of NoC applications as well as the decrease in the average latency and energy consumption.

HW/SW architecture for soft-error cancellation in real-time operating system

Today, real-time applications with critical constraints are usually run in an environment with Real-Time Operating System (RTOS). Services provided by RTOSs are severely exposed to faults which affect both functional and timing of the tasks running on the RTOS based system. In this paper, we introduce a new architecture for RTOS provides more robust services in term of Soft Errors (SEs). We evaluate and analyze robustness of the services due to SEs in two architectures, i.e. SW-RTOS and HW/SW-RTOS. Experimental results show more robust services were provided by HW/SW-RTOS versus purely SW-RTOS regarding SEs.

Hierarchical Embedded Logic Analyzer for Accurate Root-Cause Analysis

Post-silicon debugging process is aimed at locating errors not detected during the process of pre-silicon verification. Although in the post-silicon validation engineers can exploit the high speed of hardware prototype to exercise huge amount of test vectors, low level of real-time observability and controllability of signals inside the prototype is a big issue. Various Design for Debug (DFD) techniques aim to improve the observability of signals and expedite the root cause analysis of errors. Typical practical DFD approaches are based on the Embedded Logic Analysis (ELA), using a trigger unit that can effectively control when to acquire the debug data. In this paper, we propose a hierarchical trigger generator that builds a trigger unit. Additionally, it provides resourceful and compact trace information for root cause analysis. Major advantages over traditional trigger units are: 1) by keeping the trace of interactions that leads to the failure, it facilitates the process of failure localization and root-cause analysis 2) it can be tuned for the specific location of a design to avoid the huge cost related to interfacing with trace signals 3) it can get parameterized to generate several units that can be placed inside the limited area in multiple debug rounds using a time-multiplex fashion.

Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors

Nowadays, more critical applications that have stringent real-time constraint are placed and run in an environment with real-time operating system (RTOS). The provided services of RTOSs are subject to faults that affect both functional and timing of Tasks which are running based on RTOS. In this paper, we try to evaluate and analyze robustness of services due to soft-errors in two proposed architecture of RTOS which are (SW-RTOS and HW/SW- RTOS). According to experimental result we finally propose an architecture which provides more robust services in term of soft-error. Real-Time Operating System (RTOS) users desire predictable response time at an affordable cost, due to this demand Hardware/Software Real-Time Operating Systems (HW/SW-RTOS) appeared. This paper analyzes the impact of soft-errors in real-time systems running applications under purely Software RTOS versus HW/SW-RTOS. The proposed model is used to evaluate robustness of services like scheduling, synchronization time management and memory management and inter process communication in Software based RTOS and HW/SW-RTOS. Experimental results show HW/SW-RTOS provide more robust services in term of soft-err or against purely software based RTOS.