Mohammad Masum Billah

Highly Robust Flexible Oxide Thin-Film Transistors by Bulk Accumulation

We report the achievement of flexible oxide thin-film transistors (TFTs) that are highly robust under mechanical bending stress. Fabricated on solution-processed polyimide, the oxide TFTs employ the dual-gate structure with an amorphous-indium-gallium-zinc oxide (a-IGZO) semiconductor, silicon dioxide gate insulators, and molybdenum gate and source/drain electrodes. High mechanical stability is achieved by shorting the two gates together to induce bulk accumulation (BA)-a condition in which the channel accumulation layer of electrons extends the entire depth of the active layer. It is shown experimentally that the BA a-IGZO TFTs exhibit better stability under bending stress compared with single gate-driven TFTs. From TCAD simulations, the immunity to slight variations in carrier concentration under tensile strain is found to be a result of the high gate-drive intrinsic of the BA TFTs.

Analysis of Improved Performance Under Negative Bias Illumination Stress of Dual Gate Driving a-IGZO TFT by TCAD Simulation

We report the numerical simulation of the effect of a dual gate (DG) TFT structure operating under dual gate driving on improving negative bias illumination stress (NBIS) of amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs). With respect to the transfer characteristics of a-IGZO TFTs, we show a larger negative threshold voltage shift (ΔVTH) with increasing a-IGZO active layer thickness. This trend is confirmed by TCAD simulation, where the initial transfer curve is plotted under varying a-IGZO thickness keeping a constant density of states. Under varying a-IGZO thickness, TCAD simulation results confirm TFTs under DG driving shows significantly less ΔVTH shift under NBIS compared with that of single gate (SG) driving TFTs. Under 10 K seconds of NBIS, TCAD simulation results show the increase in donor-like states (NGD) by 5.25 × 1017 cm-3 eV-1 and acceptor-like states (NGA) by 7.5 × 1016 cm-3 eV-1.

TCAD Simulation of Dual-Gate a-IGZO TFTs With Source and Drain Offsets

We investigate the effect of offset between source/drain (S/D) and gate electrodes (both top gate (TG) and bottom gate (BG)) on the electrical performance of dual-gate (DG) amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). The performance of the fabricated TFTs measured by BG sweep under various TG potentials are well fitted by TCAD simulation with the same density of states, which does not change with the device structure. The field-effect mobility is 15.5 cm2/Vs for the TFT with overlapped S/D electrodes, but it is less than 1 cm2/Vs for the offset TFTs. The low carrier concentration of ~1016 cm-3 at the offset a-IGZO region is achieved by TCAD simulation, which increases the contact resistance, and thus induces current crowding and lower mobility in DG offset TFTs.

Double-Gate Modulated Corbino TFTs

Short-channel Corbino thin-film transistors (TFTs) exhibit infinite output resistance beyond pinchoff when the outer-ring electrode is biased as the drain but suffer from low drain currents. It is shown here that the employment of a thin (<;25 nm) amorphous oxide semiconductor and a double-gate (DG) structure (with a top-gate electrically tied to a bottom-gate) increases the drain currents of the Corbino TFTs biased in the outer-drain condition by over two times through bulk-accumulation (BA), without compromising their infinite output resistance beyond pinchoff or bias, temperate, and light stability. By experiment and through 3-D TCAD simulations, evidence of BA under DG modulation and the origin of the infinite output resistance beyond pinchoff in Corbino TFTs are also revealed in this letter.

Electrical stability of flexible a-IGZO TFT under strained condition

We report the effect of tensile strain on the electrical performance of flexible a-In-Ga-Z-O (a-IGZO) thin-film transistor (TFT). Positive bias stress (PBS) measurement with Vgs = 20 V and Vds = 0 V in a-IGZO TFTs show positive transfer shift due to the trapping of negative charges, likely electron trapping. We observed that tensile strained TFT with 2 mm bending radius exhibits a positive ΔVTh (V) ~2.3 V shift compared to flat condition TFT (ΔVth (V) ~1.5 V) after 3.6K seconds stress. It clearly revels that more charges are trapped at the gate insulator/a-IGZO interface when the Fermi level is shifted downward by PBS with strained geometry.