Mohd Tafir Mustaffa

A reconfigurable LNA for multi-standard receiver using 0.18 μm CMOS technology

This paper presents the design of a reconfigurable low noise amplifier (LNA) for multi-standard multi-band receiver. In this design, inductively-degenerated common-source (IDCS) topology is chosen as it has been proven to be a good choice in designing multi-standard multi-band LNA. The design is using 0.18 μm CMOS technology. The reconfigurable LNA has been designed to operate in two bands of standards consisting the bands range from 800 to 1000-MHz (lower band) and 1800 to 2200-MHz (upper band). The simulation results exhibit gain S21 of 12.9-dB for lower band and 12.4-dB for upper band, input reflection S11 of −14.5-dB and −17.2-dB for both bands, and output return loss S22 of −14.7-dB and −26-dB for lower and upper band making the LNA suitable for most of the mobile communication applications. The LNA also exhibits the noise of figure of 2.55-dB and 2.3-dB for lower and upper band respectively. The circuit consumes 26.5 mW when operating in lower band mode and uses 18.8 mW of power when operating in upper band mode.

A novel tunable water-based RF MEMS solenoid inductor

This paper proposed a novel tunable MEMS solenoid inductor. This tunable solenoid inductor benefits from a liquid-injected core which varies the permeability of the core corresponding to the level of injection of the liquid; hence, the change in permeability of the core causes the change in the inductance. In this work, HFSS is used for 3D EM simulation. The proposed Solenoid inductor is simulated in Silicon substrate with Copper metal as the coil and injected salted water (CaCl2 solved in water) as the solenoid core. The similar previous works for tunable MEMS inductor employing ferromagnetic cores and liquid-based spiral inductors could not exceed an operating frequency of 2 GHz and a Q factor of 12. Here, a maximum Q factor of 18 and tuning range of 60% were achieved at 18 GHz. Also, the implementation procedure of the proposed variable solenoid inductor is simpler and more cost-effective than the other works.

A dual-band LNA with 0.18-μm CMOS switches

This paper proposed the design of a switchable dual-band low-noise amplifier (LNA) using Silterra 0.18-μm CMOS technology fabrication process. The LNA utilized the single-ended type with cascode inductively source degeneration topology. This topology is best for simultaneous noise and input matching besides capable of reducing the Miller effect as well as improving on the reverse isolation performance. The switchable dual-band LNA can be tuned to center frequency of either 1.575 GHz for global positioning system (GPS) or 2.4 GHz for WLAN 802.11b standard applications. The LNA can cater frequency range of 1.33 to 2.10 GHz and 1.69 to 2.64 GHz for GPS and WLAN application, respectively. The switching of the operating frequency can be achieved by capacitor selection using MOS as switches at its input and output matching network. NMOS switches were implemented as they have lower on resistance and can provide larger gain when compared with PMOS. The selection of the switches is based on the voltage supplied to each switch. The supply voltage for the LNA is 1.8 V and the voltage required to enable the MOS switches is 3 V. Pre-layout simulation for input third-order intercept points (IIP3) are +1.62 dBm and +1.17 dBm for center frequency of 1.575 GHz and 2.4 GHz, respectively. Post layout simulation shows input reflection coefficients (S11) of −15 dB and −16 dB, reverse isolation coefficients (S12) of −56 dB and −50 dB, power gains (S21) of 10 dB and 11 dB, output reflection coefficients (S22) of −13 dB and −15 dB and noise figure (NF) of 3.2 dB and 3 dB for center frequency of 1.575 GHz and 2.4 GHz, respectively. Thus, the design is able to meet the requirements of the desired standards. The LNA consumes current of 18.5 mA at both 1.575 GHz and 2.4 GHz frequencies and therefore resulting a power consumption of 33.23 mW.

A switchable CMOS LNA using capacitor switching

This paper discusses a design of single path low noise amplifier (LNA) architecture with variable capacitor switching, which can switch between standards of GSM 850 MHz and GSM 1.8 GHz. The LNA is designed using Silterra 0.18 µm CMOS technology process. The inductively degenerated cascode low noise amplifier topology has been adopted to develop this switchable LNA architecture. The post-layout simulations of the multi-standard LNA at 850 MHz for the input matching S<inf>11</inf> is −12.74 dB, reverse isolation S<inf>12</inf> is −55 dB, power gain S<inf>21</inf> is 10.67 dB, and output matching S<inf>22</inf> is −15.2 dB. On the other hand, the post-layout simulations at 1.8 GHz for the input matching S<inf>11</inf> is −6.9 dB, reverse isolation S<inf>12</inf> is −43.94 dB, power gain S<inf>21</inf> is 14.13 dB, and output matching S<inf>22</inf> is −11.36 dB. The noise figure of the multi-standard LNA at 1.8 GHz is 2.64 dB and 850 MHz is 3.92 dB. The total power consumption for both frequencies is 41.6 mW. The die size is 1.65 mm × 1.80 mm.

1.575 GHz to 2.48 GHz multi-standard low noise amplifier using 0.18-µm CMOS with on-chip matching

A wideband Low Noise Amplifier (LNA) is demonstrated by using the inductively degenerated LNA architecture. This wideband operates in range of 1.575 GHz to 2.48 GHz frequency band. The design of the LNA utilizes the Power Constraint Noise Optimization (PCNO) technique in determining the device size. The simulation results achieved the maximum power gain S21 at 13.7 dB to 10.3 dB, input reflection coefficient S11 at −7.2 dB to −9.5 dB, output reflection coefficient S22 at −17 dB to −10 dB, reverse isolation S12 at −54.4 dB to −52.1 dB and noise figure (NF) at 2.31 dB to 3.12 dB in the frequency range. Linearity result is based on the Input Third-Order Intercept Point (IIP3) is −5.48 dBm. The design draws and obtained at low total power consumption at 14.4 mW and all results met specification. The design was implemented in 0.18 µm CMOS technology. The performances obtained are from the LNA with on-chip matching circuitries.

Radio-frequency silicon-based CMOS-compatible MEMS variable solenoid micro-fluidic inductor with Galinstan-based continuously-adjustable turn-ratio technique

This paper proposes a continuously-variable MEMS solenoid inductor with resonating frequency of over 8 GHz. This inductor allows high-tuning capability for resonance adjustment purpose in reconfigurable radio-frequency circuit devices. To achieve this goal, a channel is contrived to bypass the turns of the coil through the injection of a conductive liquid (here, Galinstan). Once the number of turns decreases, the inductance value falls according to the injection level. The proposed solenoid inductor is simulated using a full-wave three-dimensional electromagnetic analysis tool, HFSS, for silicon substrate with copper metallic coil for different level of conductive liquid injection. Beside the cost-effective and easy manufacturing process, the simulation results demonstrate the 150% tuning range. The EM simulation results show a maximum quality factor of 85 at 3 GHz for proposed inductor. The minimum and maximum inductance values are 1.5 and 4 nH at 4 GHz for low-resistivity Silicon. This tunable inductor can be applied into reconfigurable radio-frequency circuits and matching networks to tune the operating frequency of the system.

Multi-band tunable low noise amplifiers operating at 850MHz and 1900MHz standards

This paper presents two novel designs for narrowband tunable low-noise amplifier implementation operating at two frequency standards of 850 MHz and 1900 MHz (cellular frequencies such as GSM, CDMA and DCS standards). Both designs benefits from a simple cascode topology with tunable input and output matching networks. Two novel methods to tune the input resonating frequency are introduced: (1) switched transistor width technique, and (2) switched extra Miller and gate-source capacitances technique. Each technique shows its own pros and cons. A comparison between the post-layout simulations results of two designs is made while they are fully matched in desired frequencies. This paper also gives a comparison table between these designs and other similar works in terms of RF performance. The 0.13-μm RF CMOS tunable LNAs have a minimum and maximum power dissipations of 2 and 4 mW, respectively, depending on the tuned resonating frequency.

Asynchronous to synchronous: A design methodology

This paper presents the methodology of converting an asynchronous design to a synchronous design. As the size of transistor is shrinking, the difficulty of a design to meet the timing has increased. Continuously shrinking of transistor size from time to time has increased the on-die variation such as Process, Voltage, and Temperature (PVT) variation of the chip. Since Performance Verification (PV) or Static Timing Analysis (STA) tools is unable to accurately calculate the timing of asynchronous design, asynchronous design is required to migrate to synchronous based design for the STA tools to ensure the silicon timing can be met across PVT. A proper design methodology of converting asynchronous design to synchronous design is proposed in this paper. An Intel 8254 Programmable Interval Timer (PIT) is used as a case study. Current Intel 8254 timer is an asynchronous based design and it has approximately 12,000 gates. STA is performed after conversion and results shows the timing of synchronous design can be fully verified by STA. Additional comparison for area is made as well.

Development of Accurate BSIM4 Noise Parameters for CMOS 0.13-µm Transistors in Below 3-GHz LNA Application

With the rapid growth of communications via the Internet, the need for an effective firewall system which has not badly affect the overall network performances has been increased. In this paper, a Field Programmable Gate Array (FPGA) -based firewall system with high performance has been implemented using Network FPGA (NetFPGA) with Xilinx Kintex-7 XC7K325T FPGA. Based on NetFPGA reference router project, a NetFPGA-based firewall system was implemented. The hardware module performs rule matching operation using content addressable memory (CAM) for higher speed data processing. To evaluate system performance, throughput, latency, and memory utilization were measured for different cases using different tools, also the number of rules that an incoming packet is subjected to was varied to get more readings using both software and hardware features. The results showed that the designed firewall system provides better performance than traditional firewalls. System throughput was doubled times of the one with Linux-Iptables firewalls.

Impact of Internal Capacitance and Resistance to the Noise Parameter Performance

This paper reports preliminary investigation of internal resistance and capacitance influence to the characterized noise parameter performance. Device Under Test (DUT) for this project is fabricated using 0.13 \(\upmu \)m process technology. The observation is performed by looking directly at the measurement results of scattering parameter and noise parameter. All uncertainties related to the measurement have been removed by the means of calibration and deembedding. Data for the internal resistance and capacitance are extracted from the scattering parameter measurement. For comparison, the measurements were conducted at two sets of gate voltage (Vg) biasing, assuming noise levels are proportional to the amount of voltage stimulated. As for the result, it is found that the lower internal resistances will result in lower R\(_n\) and NFmin.