Norlaili Mohd Noh

Broadband RF feedback amplifier design with simple feedback network

The paper presents a simple and fast design technique for an RF feedback amplifier. The amplifier uses a series resistor and capacitor as the feedback element. An overview of the amplifier impedance analysis and the noise theory of the amplifier is presented. A high frequency passive component model is also presented. With a current consumption of 6 mA, the simulated amplifier features a noise figure of 2.4 dB and an S/sub 21/ of 14.7 dB at 2 GHz. It achieves a very flat S/sub 21/ over 50 MHz to 2.5 GHz.

Adaptive neuro-fuzzy inference system identification model for smart control valves with static friction

The study of static friction in control engineering is the subject of many researches due to its impact on degradation of performance of the control loops. Mathematical model of systems with static friction is not straight forward. Precise and proper model of this phenomenon is a key factor in model-based control to mitigate its effect. By increasing number of smart valve in industry, demand for identification of such valves is rising. In these valves, identification of process is limited to control signal (OP) and valve position (MV). By taking advantage of Hammerstein approach, identification is divided in two parts, linear dynamic part and nonlinear static part. In this paper, adaptive neuro-fuzzy inference system (ANFIS) is used for identification of nonlinear static part of the plant. The linear dynamic part can be identified using linear identification methods. Results reveal that ANFIS which integrates both neural networks and fuzzy logic principles and has potential to capture the benefits of both in a single framework can capture well the key model of the systems with smart valves involved in static friction.

Design, Simulation and Measurement Analysis on the S-parameters of an Inductively-degenerated Common-source Open-drain Cascode Low Noise Amplifier

An inductively-degenerated common-source (CS) open-drain cascode LNA was designed for W-CDMA application. The operating frequency for the design was at 2.14 GHz, which is at the center of the reception range of the W-CDMA standard. The supply voltage is 1.8 V at 0.18 mum CMOS process. The LNA was designed using power-constrained noise optimization method in obtaining the width of the transistor of 290 mum. Post-layout simulations with distributed resistors and capacitors were performed. On-chip inductors with quality factor of 8 were utilized to resonate with the metal-insulator-metal capacitor (mimcap). The mimcap was also used to isolate VDD and ground. The input was 50 Omega matched using the transistor as well as an inductor at the gate and three parallel 1.65 nH inductors acting as a 0.55 nH degeneration inductor at the source. Detailed design steps are described in this paper with plots of the post-layout simulation and measurement results provided. These plots are analyzed extensively in this paper and justification for the errors are given. The 12.8 dB of S21 obtained from the post-layout and a much less 7.8 dB from the measurement shows that there is an offset by 5 dB. Derivations are given to show that the unmatched output is the cause of the gain offset. S11 is measured at -24 dB which is very close to the simulated value of -25.4 dB. The current measured and simulated at a bias voltage of 0.65 V is 4.1 mA.

A novel tunable water-based RF MEMS solenoid inductor

This paper proposed a novel tunable MEMS solenoid inductor. This tunable solenoid inductor benefits from a liquid-injected core which varies the permeability of the core corresponding to the level of injection of the liquid; hence, the change in permeability of the core causes the change in the inductance. In this work, HFSS is used for 3D EM simulation. The proposed Solenoid inductor is simulated in Silicon substrate with Copper metal as the coil and injected salted water (CaCl2 solved in water) as the solenoid core. The similar previous works for tunable MEMS inductor employing ferromagnetic cores and liquid-based spiral inductors could not exceed an operating frequency of 2 GHz and a Q factor of 12. Here, a maximum Q factor of 18 and tuning range of 60% were achieved at 18 GHz. Also, the implementation procedure of the proposed variable solenoid inductor is simpler and more cost-effective than the other works.

Systematic Width Determination for the Design of Power-Constrained Noise Optimization Inductively Degenerated Low Noise Amplifier

Abstract Systematic width determination for the inductively degenerated low noise amplifier (IDLNA) was implemented using power-constrained noise optimization (PCNO) technique. Using drain current for short channel equation, the power dissipated (PD) as a function of gate overdrive (VOV) expression was derived. This expression was further arranged to represent PD as a function of input stage quality factor (QS). The two relations were translated into contours which were generated at fixed noise figure (NF). By means of manipulating the same equations, the NF as a function of QS was derived. The contours were generated using the parameters specified for Silterra’s 0.18 μm CMOS process for Wideband-Code Division Multiple Access (W-CDMA) application. The PD versus VOV contours show that the NF of the LNA can be improved if PDis increased. These contours also illustrate that for a W-CDMA with a requirement of below 2.5 dB of NF, the VOVis in the range of 46–115 mV. The PD and NF versus QS contours show that minimum PD for each NF and minimum NF at each PD is maintained at QS equal to 4, independent of the process and operating frequency. This result is verified by derivations and comparisons with a referenced article. With the optimum QS known, the calculated transistor’s width is 330 μm to provide an NF of 1 dB at 6 mW of power.

Valve stiction in control loops — A survey on effective methods of detection and compensation

In many industrial manufacturers, the quality of product heavily depends on control loop performance. Oscillations in control loop decreases performance of their systems. This is made worse with the increased number of control loops in a control process. There are several reasons for oscillations such as poor controller tuning, oscillating load or disturbances with a high-frequency. However, the most common reason for oscillations is friction in the valve. This paper presents a brief summary of some effective methods of detection of stiction in control loops and the compensation techniques to mitigate this effect. The aim is to determine the appropriate model of stiction in order to design a proper controller to prevent oscillations in the control loops. Based on the literature, Data Driven model with fewer parameters provides simpler solution and is the most common method used in comparison with physical based model which presents a number of unknown physical parameters. Moreover, previous methods (even in data-driven models) were based on some assumptions and thus their judgments are not reliable when the assumptions were not satisfied. From this study too, it is seen that numerous methods of stiction detection are available. Hence, it is suggested that the future research emphasis should be more on compensation of stiction especially for nonlinear processes.

A dual-band LNA with 0.18-μm CMOS switches

This paper proposed the design of a switchable dual-band low-noise amplifier (LNA) using Silterra 0.18-μm CMOS technology fabrication process. The LNA utilized the single-ended type with cascode inductively source degeneration topology. This topology is best for simultaneous noise and input matching besides capable of reducing the Miller effect as well as improving on the reverse isolation performance. The switchable dual-band LNA can be tuned to center frequency of either 1.575 GHz for global positioning system (GPS) or 2.4 GHz for WLAN 802.11b standard applications. The LNA can cater frequency range of 1.33 to 2.10 GHz and 1.69 to 2.64 GHz for GPS and WLAN application, respectively. The switching of the operating frequency can be achieved by capacitor selection using MOS as switches at its input and output matching network. NMOS switches were implemented as they have lower on resistance and can provide larger gain when compared with PMOS. The selection of the switches is based on the voltage supplied to each switch. The supply voltage for the LNA is 1.8 V and the voltage required to enable the MOS switches is 3 V. Pre-layout simulation for input third-order intercept points (IIP3) are +1.62 dBm and +1.17 dBm for center frequency of 1.575 GHz and 2.4 GHz, respectively. Post layout simulation shows input reflection coefficients (S11) of −15 dB and −16 dB, reverse isolation coefficients (S12) of −56 dB and −50 dB, power gains (S21) of 10 dB and 11 dB, output reflection coefficients (S22) of −13 dB and −15 dB and noise figure (NF) of 3.2 dB and 3 dB for center frequency of 1.575 GHz and 2.4 GHz, respectively. Thus, the design is able to meet the requirements of the desired standards. The LNA consumes current of 18.5 mA at both 1.575 GHz and 2.4 GHz frequencies and therefore resulting a power consumption of 33.23 mW.

A 1.4dB Noise Figure CMOS LNA for W-CDMA Application

This paper presents a 2.14 GHz low noise amplifier (LNA) intended for use in a wide-band code division multiple access (W-CDMA) receiver. The LNA has been implemented in RF 0.18mum CMOS process. The amplifier provides a forward gain (S21) of 11dB with a noise figure of only 1.4dB from a 1.8V supply voltage. The input power 1dB-compression point of the LNA is -11dBm and the input referred 3rd-order intercept point is 6.6dBm. Total power consumption is 23mW as current consumed by the circuit is 12.7mA. The LNA is differential in nature and is of the inductive source degeneration type. In this paper, detailed analysis of the LNA architecture is presented

Design of CMOS differential LNA at 2.4GHz

This paper present design and simulation of differential low noise amplifier that utilized inductively degenerated common-source (CS) open drain cascode topology. The operating frequency for the design was at 2.4GHz for IEEE 802.11b standard. The LNA has been implemented in RF 0.13um CMOS process. Power constraint noise optimization method has been used to obtain the optimized width of the transistor with a low noise figure and good power gain. Post layout simulation provides a forward gain (S21) of 18.56dB, S11 of -27.63dB with a noise figure (NF) of 1.85dB and IIP3 = -7.75. The total current consumed by the circuit is 7.59mA thus making the power consumption is 9mW.

1.575 GHz to 2.48 GHz multi-standard low noise amplifier using 0.18-µm CMOS with on-chip matching

A wideband Low Noise Amplifier (LNA) is demonstrated by using the inductively degenerated LNA architecture. This wideband operates in range of 1.575 GHz to 2.48 GHz frequency band. The design of the LNA utilizes the Power Constraint Noise Optimization (PCNO) technique in determining the device size. The simulation results achieved the maximum power gain S21 at 13.7 dB to 10.3 dB, input reflection coefficient S11 at −7.2 dB to −9.5 dB, output reflection coefficient S22 at −17 dB to −10 dB, reverse isolation S12 at −54.4 dB to −52.1 dB and noise figure (NF) at 2.31 dB to 3.12 dB in the frequency range. Linearity result is based on the Input Third-Order Intercept Point (IIP3) is −5.48 dBm. The design draws and obtained at low total power consumption at 14.4 mW and all results met specification. The design was implemented in 0.18 µm CMOS technology. The performances obtained are from the LNA with on-chip matching circuitries.