Mohit Kumar Gupta

Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell

This paper presents a Schmitt-trigger-based single-ended 11T SRAM cell, which significantly improves read and write static noise margin (SNM) and consumes low power. Simulation results show that the cell also achieves the lowest leakage power dissipation among the cells considered for comparison. We also investigate the impact of process, voltage, and temperature variations on various performance parameters, such as hold SNM, read SNM, write margin, immunity to half-select issue, ION/IOFF ratio of read path, and leakage power of the cell; Monte Carlo simulation results confirm the robustness of the proposed cell toward these issues. Layout drawn in a 45-nm technology rule shows that the proposed cell occupies 2.02× greater area as compared with 6T SRAM cells. However, 6.9× higher ION/IOFF ratio of the read path of the proposed cell as compared with 6T cell holds potential to significantly subside the area overhead. A new figure of merit that comprehensively captures stability, delay, power dissipation, and area of an SRAM cell is also proposed. Based on the proposed metric, we observe that the proposed cell outperforms all, but one of the SRAM cells considered in this paper.

Robust High Speed Ternary Magnetic Content Addressable Memory

Designing robust, low power, and delay ternary magnetic content addressable memory (TMCAM) using spintronic-based devices like magnetic tunnel junction (MTJ) is a challenge. Process variations in MTJ and transistor degrade the performance of ternary content-addressable memory (TCAM) as the number of bits increases. To bring TCAM using MTJ (TMCAM) to practical use for wide arrays (>2048 bits), its cell has to be designed with large tolerance to all types of variations. Reducing the power consumption associated with searching without the increase in delay is also essential for the designing of TMCAMs. The proposed TMCAM cell has guaranteed read-disturbance immunity, low delay, and comparable power as compared with the reported MTJ-based magnetic-content-addressable memory (MCAM). Monte Carlo simulation was performed for proving the robustness of the proposed TMCAM by considering both variations in MTJ and transistor parameters. A Verilog-A model of the MTJ along with 45-nm CMOS technology is used for the simulation. A delay reduction of 1.23 times with power decrement of 1.23 times is obtained compared with previously reported MCAM for TMR = 3. This leads to a power-delay product improvement of 1.5 times for 2048-bit TMCAM.

A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits

Advanced computing systems embed spintronic devices to improve the leakage performance of conventional CMOS systems. High speed, low power, and infinite endurance are important properties of magnetic tunnel junction (MTJ), a spintronic device, which assures its use in memories and logic circuits. This paper presents a PentaMTJ-based logic gate, which provides easy cascading, self-referencing, less voltage headroom problem in precharge sense amplifier and low area overhead contrary to existing MTJ-based gates. PentaMTJ is used here because it provides guaranteed disturbance free reading and increased tolerance to process variations along with compatibility with CMOS process. The logic gate is validated by simulation at the 45-nm technology node using a VerilogA model of the PentaMTJ.

‘Xerosis meter’: a new concept in dry eye evaluation

BackgroundDry eye is not only incapacitating to the patient but its treatment is also challenging. It would undoubtedly be more amenable to therapy if it could be detected at an early stage and its prognosis be recorded accurately and sensitively. In the past few years ‘dry eye’ and its sequelae have become the focus of attention of ophthalmologists worldwide. Whereas there has been a tremendous contribution by the pharmaceutical industry towards its treatment, its diagnostic and prognostic tests, such as Schirmer’s test and tear film break-up time (BUT), appear primitive. With this in mind, we have designed a ‘xerosis meter’—an electronic device that can detect and grade tissue dryness.MethodsThis device is based on the principle that the electrical conductivity of any tissue is directly proportional to its wetness. The sensitivity of this instrument was compared with Schirmer’s test and BUT.Result and conclusionThe xerosis meter readings in normal eyes (control group) and dry eyes (test group) were compared statistically using the unpaired t-test (p<0.001). The sensitivity of the xerosis meter (86.11%) was much higher than that of Schirmer’s test (80.55%) and BUT (66.66%).

Low Leakage Single Bitline 9T (SB9T) Static Random Access Memory

This paper presents a low leakage, half-select free SB9T SRAM cell with good static and dynamic read/write performance along with smaller area. The proposed cell offers high Read SNM and low leakage power among the cells considered in this work while causing an area overhead of only 37% of that of 6T cell. Simulation results show that the proposed cell offers 4.2x higher RSNM, 33% lower mean leakage power as compared to 6T SRAM. The proposed cell also offers more than 10x higher Ion/Ioff ratio that holds potential to compensate for the area overhead by having more number of cells connected to the same bitline. The proposed cell has longer write delay because of the single bitline structure; however, it offers lower read delay and smaller read/write power to that of the 6T cell. Monte Carlo simulations using HSPICE at 16nm technology were performed by incorporating local and global variations and it is observed that the proposed cell offers high robustness against process variations. Therefore, the proposed cell could be a good choice for applications that demand high stability, low power, low area and moderate speed.

High-Density Magnetic Flash ADC Using Domain-Wall Motion and Pre-Charge Sense Amplifiers

Unintentional shutdown of power in CMOS circuitry leads to loss of data. The usage of non-volatile elements along with CMOS to improve its performance in terms of power consumption, area, and delay is very attractive. Non-volatile elements act as a backup data source for CMOS circuitry. Current-induced domain-wall (DW) motion is a prominent switching mechanism promising low-power, high-density, and high-speed circuits. This paper presents a novel DW motion and pre-charge sense amplifier-based magnetic flash analog-to-digital converter (ADC), which is faster, and power and area efficient compared with other CMOS ADCs. By using a DW motion in a magnetic stripe SPICE compatible Verilog-A model and CMOS 45 nm design kit, its performance, such as power and delay, has been simulated and compared with CMOS-based ADCs.

SRAM enablement beyond N7: A BTI study

Operating voltage (Vmin) improvement for High density SRAM with scaling is halted due to variability and aging effects which becomes a bottleneck for energy optimized operation. Device level and cell level advancements help the SRAM in lowering Vmin. Assist techniques become beneficial in Vmin lowering but due to BTI their Vmin degrades. BTI sensitivity analysis for these solutions gives insight of BTI resilient HD SRAM design for advanced technology node.

Dedicated technology threshold voltage tuning for 6T SRAM beyond N7

As scaling continues for FinFET technology nodes, variability in combination with targeted lower supply voltages results in reduced SRAM stability margins. In this paper, threshold voltage tuning from the technological side is used to enable low SRAM Vmin with minimum impact on logic performance. Furthermore, lower overall system energy consumption can be achieved by the lower Vmin. This exercise is crucial for the enablement of future technology nodes where single VTH masks could become a necessity.

Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7

SRAM paves the way for new technology nodes as it is more prone to failure due to intrinsic devices variability and technology process. To further boost high density SRAM yield and performance we need assist techniques and increased SRAM bit cell size at the expense of area. This paper discusses SRAM design strategies for future technologies nodes like beyond the N7 node, by comparing higher height cells and assist techniques. Although, higher height cells improve variability with scaled nodes but also need assist techniques to lower the operating voltage. Consequently, 122 is shown to meet the yield requirement and the preferred option to use with and without assist circuitry.

Self-Terminated Write-Assist Technique for STT-RAM

The main challenge in the programming of spin transfer torque (STT)-RAM is to reduce the associated power consumption without the increase in area. This paper proposes a novel self-terminated write-assist technique to cutoff the unnecessary writing power consumption and then compares its delay and writing power consumption with the previously reported technique along with the area required. Programming of magnetic random access memory array is done by bi-directional current flow (i.e., STT) that enables high density along with write monitoring system for determining the write termination. A Verilog-A compact model of the magnetic tunnel junction along with 45-nm CMOS technology is used for the simulation. Monte Carlo simulation is performed for proving the robustness of the proposed design. An energy and area reduction, of up to 41% and 67%, respectively, with the same delay, are obtained compared with the previously reported technique.