Mohit Pathak

3D-MAPS: 3D Massively parallel processor with stacked memory

Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration, but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM. Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5x5mm2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm2 power density. The core architecture is developed from scratch to benefit from single-cycle access to SRAM.

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory

We describe the design and analysis of 3D-MAPS, a 64-core 3D-stacked memory-on-processor running at 277 MHz with 63 GB/s memory bandwidth, sent for fabrication using Tezzarons 3D stacking technology. We also describe the design flow used to implement it using industrial 2D tools and custom add-ons to handle 3D specifics.

Through-silicon-via management during 3D physical design: when to add and how many?

In 3D integrated circuits through silicon vias (TSVs) are used to connect different dies stacked on top of each other. These TSV occupy silicon area and have significantly larger area than regular gates. In this paper, we address two critical aspects of TSV management in 3D designs. First, we address the problem of how many TSVs to add in a design. Since TSVs occupy significant silicon area, a general tendency has been to use a minimum number of TSVs in 3D circuits. We show that such an approach does not give us the best possible result. Second, we address the problem of TSV insertion. Because TSVs occupy silicon area, their location is decided during the placement stage of 3D design. However, we show that this is not the best possible stage for TSV insertion. We propose a change in the physical design flow for 3D integrated circuits to address the limitations of existing TSV placement methodology. All our algorithms are integrated with commercial tools, and our results are validated based on actual GDSII layouts. Our experimental results show the effectiveness of our methods.

Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs

Electromigration (EM) is a critical problem for interconnect reliability of modern integrated circuits (ICs), especially as the feature size becomes smaller. In three-dimensional (3D) IC technology, the EM problem becomes more severe due to drastic dimension mismatches between metal wires, through silicon vias (TSVs), and landing pads. Meanwhile, the thermo-mechanical stress due to the TSV can also cause reduction in the failure time of wires. However, there is very little study on EM issues that consider TSVs in 3D ICs. In this paper, we show the impact of TSV stress on EM failure time of metal wires in 3D ICs. We model the impact of TSV on stress variation in wires. We then perform detailed modeling of the impact of stress on EM failure time of metal wires. Based on our analysis, we build a detailed library to predict the failure time of a given wire based on current density, temperature and stress. We then propose a method to perform fast full-chip simulation, to determine the various EM related hot-spots in the design. We also propose a simple routing-blockage scheme to reduce the EM related failures near the TSVs, and see its impact on various metrics.

Modeling of electromigration in through-silicon-via based 3D IC

Electromigration (EM) is a critical problem for interconnect reliability of modern IC design, especially as the feature size becomes smaller. In 3D IC technology, the EM problem becomes more severe due to drastic dimension mismatches between metal wires, through-silicon-vias (TSVs), and landing pads. Meanwhile, the thermo-mechanical stress due to TSV can further interact with EM and shorten the lifetime of the structure. However, there is very little study on EM issues with respect to TSV for 3D ICs. In this paper, we perform detailed and systematic studies on: (1) EM lifetime modeling of TSV structure, (2) impact of TSV stress on EM lifetime of BEOL wires, and (3) EM-robust design guidelines for TSV-based 3D ICs. Our results show EM-induced lifetime of TSV structure and neighboring wire largely depend on the TSV-induced stress. Also, lifetime of a wire can vary significantly depending on the relative position with the nearby TSV.

Thermal-aware Steiner routing for 3D stacked ICs

In this paper, we present the first work on the Steiner routing for 3D stacked ICs. In the 3D Steiner routing problem, the pins are located in multiple device layers, which makes it more general than its 2D counterpart. Our algorithm consists of two steps: tree construction and tree refinement. Our tree construction algorithm builds a delay-oriented Steiner tree under a given thermal profile. We show that thermal-aware 3D tree construction involves the minimization of two-variable Elmore delay function. In our tree refinement algorithm, we reposition the through-vias while preserving the original routing topology for further thermal optimization under performance constraint. We employ a novel scheme to relax the initial NLP formulation to ILP and consider all through-vias from all nets simultaneously. Our related experiments show the effectiveness of our proposed solutions.

Design for manufacturability and reliability for TSV-based 3D ICs

The 3D IC integration using through-silicon-vias (TSV) has gained tremendous momentum recently for industry adoption. However, as TSV involves disruptive manufacturing technologies, new modeling and design techniques need to be developed for 3D IC manufacturability and reliability. In particular, TSVs in 3D IC may cause significant thermal mechanical stress, which not only results in systematic mobility/performance variations, but also leads to mechanical reliability concerns such as interfacial cracking. Meanwhile, the huge dimensional gaps between TSV, on-chip wires, and bonding/packaging all lead to new electromigration concerns. Thus full-chip/package modeling and physical design tools need to be developed to achieve more reliable 3D IC integration. In this paper, we will discuss some key design for manufacturability and reliability challenges and possible solutions for TSV-based 3D IC integration, as well as future research directions.

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)

This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2 \microm-diameter, 6 \micro m-height through-silicon vias (TSVs) and 3.4\nbsp\microm-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks.

Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs

In this paper, we present a performance and thermal-aware Steiner routing algorithm for three-dimensional (3-D) stacked integrated circuits. Our algorithm consists of two steps: tree construction and tree refinement. Our tree construction algorithm builds a delay-oriented Steiner tree under a given thermal profile. We show that our 3-D tree construction involves minimization of two-variable Elmore delay function. In our tree refinement algorithm, we reposition the through-silicon-vias (TSVs) used in existing Steiner trees while preserving the original routing topology for further thermal optimization under a performance constraint. We employ a novel scheme to relax the initial nonlinear programming formulation to integer linear programming and consider all TSVs from all nets simultaneously. Our tree construction algorithm outperforms the popular 3-D maze routing by 52% in terms of performance at the cost of 15% wirelength and 6% TSV count increase for four-die stacking. In addition, our TSV relocation results in 9% maximum-temperature reduction at no additional area cost. We also provide extensive experimental results, including the following: (1) the wirelength and delay distribution of various types of 3-D interconnects; (2) the impact of TSV RC parasitics on routing and TSV relocation; and (3) the impact of various bonding styles on routing and TSV relocation. Last, we provide results on two-die stacking.

Physical layout automation for system-on-packages

System-On-Package (SOP) technology provides a capability to integrate both mixed-signal active components and passive components all into a single high speed/density three dimensional packaging substrate. The physical layout resource of SOP is multi-layer in nature, where all layers are used for both placement and routing unlike the traditional multi-layer PCB or MCM packaging. In this paper, we present the first 3D physical design algorithms targeting SOP technology. 3D partitioning divides the input design into multiple layers. 3D placement determines the location of the active and passive components in multi-layer packaging substrate while considering various signal integrity issues. 3D global routing performs the following major steps: pin/net distribution, layer assignment, tree generation, and channel/pin assignment. Our experimental results demonstrate the effectiveness of our approaches.