Moongon Jung

3D-MAPS: 3D Massively parallel processor with stacked memory

Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration, but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM. Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5x5mm2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm2 power density. The core architecture is developed from scratch to benefit from single-cycle access to SRAM.

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory

We describe the design and analysis of 3D-MAPS, a 64-core 3D-stacked memory-on-processor running at 277 MHz with 63 GB/s memory bandwidth, sent for fabrication using Tezzarons 3D stacking technology. We also describe the design flow used to implement it using industrial 2D tools and custom add-ons to handle 3D specifics.

TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC

In this paper, we propose an efficient and accurate full-chip thermomechanical stress and reliability analysis tool and design optimization methodology to alleviate mechanical reliability issues in 3-D integrated circuits (ICs). First, we analyze detailed thermomechanical stress induced by through-silicon vias in conjunction with various associated structures such as landing pad and dielectric liner. Then, we explore and validate the linear superposition principle of stress tensors and demonstrate the accuracy of this method against detailed finite element analysis simulations. Next, we apply this linear superposition method to full-chip stress simulation and a reliability metric named the von Mises yield criterion. Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3-D ICs. Our numerical experimental results demonstrate the effectiveness of the proposed methodology.

Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC

In this work, we propose an efficient and accurate full-chip through-silicon-via (TSV) interfacial crack analysis flow and design optimization methodology to alleviate TSV interfacial crack problems in 3D ICs. First, we analyze TSV interfacial crack at TSV/dielectric liner interface caused by TSV-induced thermo-mechanical stress. Then, we explore the impact of TSV placement in conjunction with various associated structures such as landing pad and dielectric liner on TSV interfacial crack. Next, we present a full-chip TSV interfacial crack analysis methodology based on design of experiments (DOE) and response surface method (RSM). Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3D ICs.

A study of IR-drop noise issues in 3D ICs with through-silicon-vias

With the extensive research on through-silicon-via (TSV) and die-stacking technology from both academia and industry, mainstream production of 3D ICs is expected in a near future. However, power delivery is believed to be one of the most challenging problems in 3D ICs. A main objective of the 3D power/ground (P/G) network optimization is to minimize the usage of P/G TSVs while satisfying power supply noise constraint. P/G TSVs consume a considerable amount of routing resources unless designed carefully. In this work, we first investigate the impact of P/G TSVs on the power supply noise as well as 3D IC layouts. We perform sign-off static IR-drop analysis on GDSII layouts of 2D and 3D IC designs using commercial-grade tools. We also explore the impact of 3D P/G network topology on IR-drop by varying P/G TSV pitch. Next, we propose a non-regular P/G TSV placement algorithm to further reduce the number of P/G TSVs used while satisfying the given IR-drop noise requirement. Compared with the conventional regular structure, our non-regular P/G TSV placement algorithm reduces the P/G TSV count, wirelength, and footprint area by 59.3%, 3.4%, and 3.5% on average, respectively.

On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective

Low power is widely considered as a key benefit of 3D ICs, yet there have been few thorough design studies on how to maximize power benefits in 3D ICs. In this paper, we present design methodologies to reduce power consumption in 3D ICs using a large-scale commercial-grade microprocessor (OpenSPARC T2). To further improve power benefits in 3D ICs on top of the traditional 3D floor-planning, we study the impact of block folding and bonding styles. We also develop an effective method to place face-to-face vias for our 2-tier 3D design for power optimization. With aforementioned methods combined, our 3D designs provide up to 20.3% power reduction over the 2D counterpart under the same performance.

Design for manufacturability and reliability for TSV-based 3D ICs

The 3D IC integration using through-silicon-vias (TSV) has gained tremendous momentum recently for industry adoption. However, as TSV involves disruptive manufacturing technologies, new modeling and design techniques need to be developed for 3D IC manufacturability and reliability. In particular, TSVs in 3D IC may cause significant thermal mechanical stress, which not only results in systematic mobility/performance variations, but also leads to mechanical reliability concerns such as interfacial cracking. Meanwhile, the huge dimensional gaps between TSV, on-chip wires, and bonding/packaging all lead to new electromigration concerns. Thus full-chip/package modeling and physical design tools need to be developed to achieve more reliable 3D IC integration. In this paper, we will discuss some key design for manufacturability and reliability challenges and possible solutions for TSV-based 3D IC integration, as well as future research directions.

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)

This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2 \microm-diameter, 6 \micro m-height through-silicon vias (TSVs) and 3.4\nbsp\microm-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks.

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core

Low power is considered by many as the driving force for 3D ICs, yet there have been few thorough design studies on how to reduce power in 3D ICs. In this paper, we discuss design methodologies to reduce power consumption in 3D IC designs using a commercial-grade CPU core (OpenSPARC T2 core). To demonstrate power benefits in 3D ICs, four design techniques are explored: (1) 3D floorplanning, (2) metal layer usage control for intra-block-level routing, (3) dual-Vth design, and (4) functional unit block (FUB) folding. With aforementioned methods combined, our 2-tier 3D designs provide up to 52.3% reduced footprint, 25.5% shorter wirelength, 30.2% decreased buffer cell count, and 21.2% power reduction over the 2D counterpart under the same performance.

Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs

In this work, we propose a fast and accurate chip/package thermo-mechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also present a design optimization methodology to alleviate mechanical reliability issues in 3D IC. First, we analyze the stress induced by chip/package interconnect elements, i.e., TSV, μ-bump, and package bump. Second, we explore and validate the principle of lateral and vertical linear superposition of stress tensors (LVLS), considering all chip/package elements. This linear superposition principle is utilized to perform full-chip/package-scale stress simulations and reliability analysis. Finally, we study the mechanical reliability issues in practical 3D chip/package designs including wide-I/O and block-level 3D ICs.