Mohiuddin Mazumder

Experimental validation of crosstalk simulations for on-chip interconnects using S-parameters

Since the design of advanced microprocessors is based on simulation tools, accurate assessments of the amount of crosstalk noise are of paramount importance to avoid logic failures and less-than-optimal designs. With increasing clock frequencies, inductive effects become more important, and the validity of assumptions commonly used in simulation tools and approaches is unclear. We compared accurate experimental S-parameters with results derived from both magneto-quasi-static and full-wave simulation tools for simple crosstalk structures with various capacitive and inductive couplings, in the presence of parallel and orthogonal conductors. Our validation approach made possible the identification of the strengths and weaknesses of both tools as a function of frequency, which provides useful guidance to designers who have to balance the tradeoffs between accuracy and computation expenses for a large variety of cases

A novel technique for full-wave modeling of large-scale three-dimensional high-speed on/off-chip interconnect structures

This paper presents a novel, rigorous, and fast method for full-wave modeling of high-speed interconnect structures. In this method, the original wave propagation problem is represented into a generalized eigenvalue problem. The resulting eigenvalue representation can comprehend conductor and dielectric losses, arbitrary dielectric and conductor configurations, and arbitrary materials such as dispersive, and anisotropic media. The edge basis function is employed to accurately represent the unknown field, and the triangular element is adopted to flexibly model arbitrary geometry. A mode-matching technique applicable to lossy system is developed to solve large-scale 3D problems by using 2D-like CPU time and memory. A circuit-based extraction technique is developed to obtain S-parameters from the unknown fields. The proposed technique can generate S-parameters, full-wave RLGC, propagation constants, characteristic impedances, voltage, current, and field distributions, and hence yield a comprehensive representation of interconnect structures. Experimental and numerical results demonstrate its accuracy and efficiency.

Experimental validation of crosstalk simulations for on-chip interconnects at high frequencies using S-parameters

Since advanced microprocessors are designed based on simulation tools, accurate assessments of the amount of crosstalk noise are of paramount importance to avoid logic failures and less-than-optimal designs. With increasing clock frequencies, inductive effects become more important, and the validity of assumptions commonly used in simulation tools and approaches is unclear. We compared accurate experimental S-parameters with results derived from both magneto-quasi-static and fullwave simulation tools, for simple crosstalk structures with various capacitive and inductive couplings, in the presence of parallel and orthogonal conductors. Our validation approach made possible the identification of the strengths and weaknesses of both tools as a function of frequency, which provides useful guidance to designers who have to balance the trade-offs between accuracy and computation expenses for a large variety of cases.

High speed differential I/O overview and design challenges on Intel enterprise server platforms

In this paper, the high speed differential I/O buses which are used on Intel server platforms are explored. The characteristics of channel components are examined along with channel and I/O circuit design challenges. Statistical time domain and frequency domain methods are briefly discussed as start-of-art simulation tools.

An Accurate and Efficient Link Analysis Methodology for High Speed I/O Design

This paper describes an accurate and efficient analysis methodology that enables circuit optimization directly guided by platform-level metric such as link eye margin. Prior to this work, such analysis was not feasible due to significant compute time required by complex circuit simulations. A new method of developing highly abstracted behavioral models of complex circuit blocks is a critical element of this analysis methodology. The method uses statistical signaling analysis and optimization capabilities coupled with behavioral modeling of I/O clocking, transmitter and receiver circuitry that are based on accurate circuit simulations. We also present measured data from products and test chips that show correlation between measured and modeled data within 10–15%. Finally, we describe how the methodology was used to optimize the design of a high speed serial link and achieve approximately 70% improvement in eye margins with limited design iterations.Copyright