M. Harmes

Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology

The authors report the first demonstration of integrating wafer stacking via Cu bonding with strained-Si/low-k 65-nm CMOS technology. Sets of 330 mm wafers with active devices such as 65-nm MOSFETs and 4-MB SRAMs were bonded face-to-face using copper pads with size ranging between 5 /spl mu/m/spl times/5 /spl mu/m and 6 /spl mu/m/spl times/40 /spl mu/m. The top wafers were thinned to different thicknesses in the range 5 to 28 /spl mu/m. Through-silicon-vias (TSVs) and backside metallization were used to enable electrical testing of both wafers in the Cu-stacked configuration. We tested individual transistors in the thinned silicon of bonded wafer pairs where the thinned silicon thickness ranged from 14 to 19 /spl mu/m. All results showed that both n- and p-channel transistors preserved their electrical characteristics after Cu bonding, thinning, and TSV integration. We also demonstrated the functionality of stacked 65-nm 4-MB SRAMs by independently testing the cells in both the thinned wafer and the bottom wafer. For the SRAM, we tested a wider thinned wafer thickness range from 5 to 28 /spl mu/m. On all tested samples, we did not find any impact to the electrical performance of the arrays resulting from the three-dimensional (3-D) integration process. The stacked SRAM is an experimental demonstration of the use of 3-D integration to effectively double transistor packing density for the same planar footprint. The results presented in this letter enable further exploratory work in high-performance 3-D logic, which takes advantage of the improved interconnect delays offered by this Cu-bonding stacking scheme integrated with modern CMOS processes.

Experimental validation of crosstalk simulations for on-chip interconnects using S-parameters

Since the design of advanced microprocessors is based on simulation tools, accurate assessments of the amount of crosstalk noise are of paramount importance to avoid logic failures and less-than-optimal designs. With increasing clock frequencies, inductive effects become more important, and the validity of assumptions commonly used in simulation tools and approaches is unclear. We compared accurate experimental S-parameters with results derived from both magneto-quasi-static and full-wave simulation tools for simple crosstalk structures with various capacitive and inductive couplings, in the presence of parallel and orthogonal conductors. Our validation approach made possible the identification of the strengths and weaknesses of both tools as a function of frequency, which provides useful guidance to designers who have to balance the tradeoffs between accuracy and computation expenses for a large variety of cases

A novel technique for full-wave modeling of large-scale three-dimensional high-speed on/off-chip interconnect structures

This paper presents a novel, rigorous, and fast method for full-wave modeling of high-speed interconnect structures. In this method, the original wave propagation problem is represented into a generalized eigenvalue problem. The resulting eigenvalue representation can comprehend conductor and dielectric losses, arbitrary dielectric and conductor configurations, and arbitrary materials such as dispersive, and anisotropic media. The edge basis function is employed to accurately represent the unknown field, and the triangular element is adopted to flexibly model arbitrary geometry. A mode-matching technique applicable to lossy system is developed to solve large-scale 3D problems by using 2D-like CPU time and memory. A circuit-based extraction technique is developed to obtain S-parameters from the unknown fields. The proposed technique can generate S-parameters, full-wave RLGC, propagation constants, characteristic impedances, voltage, current, and field distributions, and hence yield a comprehensive representation of interconnect structures. Experimental and numerical results demonstrate its accuracy and efficiency.

Experimental validation of crosstalk simulations for on-chip interconnects at high frequencies using S-parameters

Since advanced microprocessors are designed based on simulation tools, accurate assessments of the amount of crosstalk noise are of paramount importance to avoid logic failures and less-than-optimal designs. With increasing clock frequencies, inductive effects become more important, and the validity of assumptions commonly used in simulation tools and approaches is unclear. We compared accurate experimental S-parameters with results derived from both magneto-quasi-static and fullwave simulation tools, for simple crosstalk structures with various capacitive and inductive couplings, in the presence of parallel and orthogonal conductors. Our validation approach made possible the identification of the strengths and weaknesses of both tools as a function of frequency, which provides useful guidance to designers who have to balance the trade-offs between accuracy and computation expenses for a large variety of cases.

Demonstration of a reliable high-performance and yielding Air gap interconnect process

Capacitance coupling in copper low-k interconnects can be further reduced by implementing Air gaps in the intra-layer dielectric. This paper describes the evaluation of an integrated Air gap technology using 32 and 22 nm node technology vehicles. Electrical, reliability, and yield results are presented.

Demonstration of an electrically functional 34 nm metal pitch interconnect in ultralow-k ILD using spacer-based pitch quartering

The patterning of a 34 nm metal pitch interconnect was realized using a spacer-based pitch quartering scheme. The pattern is transferred into an ultralow-k ILD using a process that avoids ILD buckling and structure collapse. Resulting features were metallized with copper, and electrically characterized. Measurement results show expected trends with drawn dimensions.

Demonstration of a 12 nm-half-pitch copper ultralow-k interconnect process

A process to achieve 12 nm half-pitch interconnect structures in ultralow-k interlayer dielectric (ILD) is realized using standard 193 nm lithography. An optimized pattern transfer that minimizes unwanted distortion of ILD features is followed by copper fill. Electrical measurements that validate functionality of the drawn structures are presented.

Resistance and electromigration performance of 6 nm wires

A process to achieve 6 nm minimum dimension interconnect wires is realized using standard 193 nm lithography. Various metals including copper are optimized to gap fill features, and tested for electrical performance and reliability. Measurements showing line electrical resistance and electromigration as functions of material, conducting area, and interfaces are presented.

Demonstration of a sidewall capacitor to evaluate dielectrics and metal barrier thin films

A sidewall planar capacitor (SW CAP) vehicle is developed to closely simulate processing conditions for metal barrier and dielectric in an integrated structure. For a known tantalum barrier for copper on a low-K dielectric, SW CAP TDDB is similar to those measured on an integrated vehicle. SW CAP results are useful for comparing electrical reliability of different dielectric systems, and effective in determining physical continuity of copper metal barriers.

Demonstration of new planar capacitor (PCAP) vehicles to evaluate dielectrics and metal barrier thin films

Planar capacitors can quickly test material properties of metals and dielectrics for interconnects. A sidewall capacitor device is used to evaluate metal thin-film barriers. Etch stop planar capacitors in turn can test multi-layer etch stops, exposing differences between leaky and good etch stop films. Fillable planar capacitors are also fabricated and results presented for that class of fill materials.