Molin Chang

A waveform‐based gate‐level timing simulator (BTS) for MOS VLSI circuits with the considerations of the internal charge effects

Abstract This paper describes an accurate and efficient gate‐level timing simulator that can give the waveform at each node of the circuit. Its high accuracy is attributed to a sophisticated delay model, which includes an accurate representation of the waveform, a consistent and meaningful definition of delay, a consideration of waveform slope effects at both input and output of a gate, a consideration of the multiple charging/discharging paths in the circuit, and a consideration of the various fan‐out and cell‐size effects. In order to represent the waveform accurately, the switching delay and the slope are defined and calculated carefully with the consideration of internal charges. In order to compute the waveform accurately, the effects of internal charges are investigated and a merged PN tree is used to represent a CMOS gate. Characteristics of the PN tree are described and the methods used to evaluate conducting paths are proposed. After the conducting paths are obtained, a recursive algorithm can be...

Recursive algorithms based on MTB tree for estimating delays in RC tree circuits considering charge sharing effect

Internal charges will affect the delay behaviour of a CMOS gate. A Modified Threaded Binary (MTB) tree and two recursive algorithms, ECS and EER, are proposed to solve this problem. The charge sharing effect, which takes place among the internal nodes, is also considered in the algorithm ECS.

Improvement in radiation-hard CMOS logic gates for noise margin

A design technique for fundamental CMOS logic gates that are almost insensitive to noise margin is proposed. An auxiliary circuit is added to the conventional CMOS logic gates. All the circuits are simulated by HSPICE. It is observed from simulation results that good radiation hard behavior appears in the improved inverter, NOR and NAND gates for noise margin, especially for the scaling down on supply voltage V/sub DD/.