Sagar Ray

High speed photodiodes in standard nanometer scale CMOS technology: a comparative study

This paper compares various techniques for improving the frequency response of silicon photodiodes fabricated in mainstream CMOS technology for fully integrated optical receivers. The three presented photodiodes, Spatially Modulated Light detectors, Double, and Interrupted P-Finger photodiodes, aim at reducing the low speed diffusive component of the photo generated current. For the first photodiode, Spatially Modulated Light (SML) detectors, the low speed current component is canceled out by converting it to a common mode current driving a differential transimpedance amplifier. The Double Photodiode (DP) uses two depletion regions to increase the fast drift component, while the Interrupted-P Finger Photodiode (IPFPD) redirects the low speed component towards a different contact from the main fast terminal of the photodiode. Extensive device simulations using 130 nm CMOS technology-parameters are presented to compare their performance using the same technological platform. Finally a new type of photodiode that uses triple well CMOS technology is introduced that can achieve a bandwidth of roughly 10 GHz without any process modification or high reverse bias voltages that would jeopardize the photodetector and subsequent transimpedance amplifier reliability.

A 10 Gb/s Inductorless AGC Amplifier With 40 dB Linear Variable Gain Control in 0.13

This work presents an inductorless, 10 Gbps automatic gain control (AGC) circuit including a speed enhanced variable gain amplifier (VGA), a power detector, a comparator, and a novel exponential function generator for extended dBlinear performance. Third-order interleaved feedback technique is utilized in the current steering VGA stage to achieve 10 Gb/s operation without using on-chip inductors. A stagger-tuned switching architecture for CMOS exponential function generation is proposed to achieve a dB-linear gain control range of ~40 dB with better than ±1 dB gain error. The relationship between tuning range and approximation error is analyzed and a novel current ratio generator circuit is proposed to implement the approximation functions in the current domain. The AGC circuit achieves a highest data rate of 10 Gb/s for 231-1 PRBS input, maintaining 360 mVp-p constant differential output with a BER <;10-12 for an input dynamic range of ~24 dB (15-240 mVp-p). Fabricated in IBM 0.13 μm CMOS technology, the chip draws 50 mW from a 1.2 V power supply (excluding the output buffer) and occupies an active area of 0.4 mm2.

\upmu \text{m}

This paper presents a speed-optimized large area avalanche photodetector (APD) in standard CMOS technology for visible light communication applications (VLC). Recent research efforts have reported high speed CMOS APDs with low breakdown voltage for considerably small photodiode sizes, which limits the APD usage in low cost optical receivers for VLC. The speed of a large-area APD dramatically decreases due to increased transit time of diffusive carriers in charge neutral regions. The proposed technique divides the active area into multiple sub-sections to decrease transit time and increase speed. A prototype 350×350 μm2 APD is fabricated in 0.13-μm CMOS technology. The photodetector achieves a maximum gain of 7.6 K at 11 V reverse bias, showing excellent agreement with simulation results as calculated using the nonlocal impact ionization model based on recursive dead-space multiplication theory (DSMT). 2-D device level simulations validate the speed enhancement by comparing the small signal simulation results of three P+/N-well photodiodes with the same area detector composed of different number of sub-sections.

CMOS

This letter presents an ON-OFF-keying visiblelight-communication (VLC) link realized over 6-m distance. The transmitter is implemented with a commercially available red LED source at 650 nm. While most of the reported high-performance VLC links are using p-insulator-n photodetectors, this receiver employs a simple CMOS-compatible p-n photo-detector. A 150-Mb/s optical wireless transmission is measured with a bit-error rate of 1.3 × 10-6, which falls below the forward error correction limit of 3.8 × 10-3. The secondorder L-C-R equalization is used in both the transmitter and the receiver circuits to achieve maximum bandwidth extension. The VLC link is realized with a low illuminance of 250 lux. This power is below the common indoor illumination levels which enables advanced lighting-compatible VLC applications. The receiver and the source circuits consume around 240 and 105 mW, respectively, which represents to our knowledge a record energy-per-bit level of 2.3 nJ/b.

Speed optimized large area avalanche photodetector in standard CMOS technology for visible light communication

An inductorless 10 Gb/s optical receiver including a novel transimpedance amplifier (TIA) with dual feedback loop and a limiting amplifier (LA) with third-order nested feedback is presented. The current-buffer based TIA employs an active Cherry-Hooper (CH) stage in the auxiliary amplifier and reuses the tail current source to achieve 10 Gbps operation in the presence of a 1pF photodiode input capacitance. The use of nested feedback in the four stage limiting amplifier enables a gain-bandwidth-product (GBP)>1THz without the use of area-consuming inductors. Implemented in IBM 130nm CMOS technology, the optical receiver achieves a BER<;10-12 at 10 Gbps for an input current of 30 μA, delivering 600 mV p-p at the output of the 50 Ω buffer. Optical testing confirmed a -13.8 dBm sensitivity for a data rate of 7.5 Gbps, mainly limited by the 850nm source used for measurement. The receiver dissipates 108mW from a 1.2V supply, while occupying a core area of only 0.08 mm2.

A 6-m OOK VLC Link Using CMOS-Compatible p-n Photodiode and Red LED

This work presents a single link CMOS high data rate receiver to be integrated in imaging diversity sensor arrays for optical wireless communication targeting indoor scenarios. To compete with existing radio frequency links, sensing and transmitting data in the hundreds of Mbits per second and above, the proposed data/light sensor is optimized at both the photodetector and circuit levels to provide 5Gps data rate from a single optical link using low cost, high yield standard CMOS technology. A novel photo-detector structure, Triple Well Interrupted N-finger photodiode, is proposed that can achieve a bandwidth up to 10 GHz at 1.2V reverse bias. To compensate for the decreased responsivity of the photodiode, a wideband, high gain and low noise transimpedance amplifier compatible with the speed-enhanced CMOS photodiode is implemented in 0.13μm CMOS technology. The amplifier chain achieves a measured bit error rate (BER) of 10-12 at 5 Gbps corresponding to 2.8μA input current in presence of 1pF input capacitance representing the photodiode. The die area is 1106μm×895μm including a transimpedance amplifier (TIA), limiter and buffer and the power dissipation is 68mW from a 1.5V DC supply.

A 15-mW 7-GHz inductorless transimpedance amplifier and a 1-THz+ GBP limiting amplifier for 10GbE optical receivers

This paper presents a free-space 4-channels imaging multiple-input multiple-output (MIMO) system for On-Off-Keying (OOK) Visible-Light-Communication (VLC) links. An aggregate data-rate of 600 Mb/s is measured over 6 meters link distance with a bit-error-rate (BER) below 10−3 with the 4-channels simultaneously modulated. While the majority of published VLC works to date use components-off-the-shelf (COTS) PIN or Avalanche PDs that require both non-standard and/or higher cost fabrication processes as well as high reverse bias potential, the presented receiver in this paper employs a 2×2 on-chip Nwell/Psub photodiodes (PD) array fabricated in a low cost CMOS-compatible process. To extract high data rate performance out of the proposed CMOS low speed PD array, a 2nd-order LCR equalization is used to compensate for the stringent bandwidth limitation of the PD, measured around 20 MHz and push the speed up to 150 Mbps/channel. With a red light-emitting-diode (LED) array at 650 nm, the 4-channels MIMO setup DC power consumption is 1.38 W, which represents to our knowledge an energy-per-bit record performance for OOK VLC systems of 2.3 nJ/bit.

CMOS integrated high speed light sensors for optical wireless communication applications

This paper describes the design and implementation of a linear optical receiver front-end for short range optical communication applications in 0.13-μm CMOS technology. While conventional optical receivers are typically implemented using limiting amplifiers (LA), emerging optical systems are expected to employ advanced modulation schemes, which require preserving the signal envelope. The proposed linear optical receiver architecture utilizes super-Gm transimpedance amplification with common-mode restoration and constant settling time automatic gain control (AGC) with background illumination cancellation to preserve the signal linearity while tolerating capacitance up to 15 pF for large area photo-detectors. Linearity aware design of transimpedance amplifiers (TIA), variable gain control (VGA), and post amplifiers (PA) are discussed before introducing an exponential generator based on the parasitic BJTs available in the used technology. Consuming 40 mW from a 1.2 V supply in the presence of ~15 pF input capacitance, the circuit achieves a binary modulation data rate of 5 Gbps with an input sensitivity of ~ 65 μA maintaining a bit-error rate (BER) <; 10-12. S-parameter measurements show a constant -3 dB bandwidth of 2.5 GHz for a wide dynamic range of ~45 dB (30-75 dBΩ) with dB-linearity error better than ±1 dB. To demonstrate the optical functionality of the architecture, an external photodiode (PDCS70T-GS) is directly wirebonded to the chip. Optical measurements confirm a sensitivity of -9.5 dBm (BER <; 10-12) at a highest data rate of 5 Gb/s (λ = 680 nm). The noise and linearity performance of the receiver is verified using input referred integrated noise and 1 dB-compression point measurements for different gain settings.

A meter-scale 600-Mb/s 2×2 imaging MIMO OOK VLC link using commercial LEDs and Si p-n photodiode array

This paper presents an inductorless, 10Gbps automatic gain control (AGC) circuit including a speed enhanced variable gain amplifier (VGA), a power detector, a comparator and a switching exponential function generator for extended dB-linear performance. Third order interleaved feedback technique is utilized to enhance the speed of the current steering VGA stage. A stagger-tuned switching architecture for CMOS exponential function generation is utilized to achieve a dB-linear gain control range of 45dB with better than ±0.5 dB gain error. The AGC circuit achieves a maximum data rate of 10 Gbps for 231-1 PRBS input, maintaining 360mVp-p constant differential output with a BER <; 10-12 for an input dynamic range of ~24 dB (15mVp-p to 240mVp-p). Fabricated in IBM 0.13-μm CMOS technology, the chip draws 50 mW from a 1.2 V power supply (excluding output buffer) and occupies an active area of 0.4 mm2.

A 30–75

This paper presents an adaptive equalizer based on dual-loop balancing technique and a third order nested feedback equalizing filter to achieve data rate up to 10Gb/s without using inductors. A spectral balancing circuit adjusts the equalizer boost, while a second servo loop automatically tracks the data rate using self-calibration and re-tunes the filters for optimal equalization. Third order nested feedback is introduced in the equalizing filters to compensate for ~15dB channel loss for a highest data rate of 10Gb/s. Implemented in IBM 0.13-μm CMOS technology, the equalizer maintains an eye opening of 0.26, 0.44 and 0.5UI with BER<;10-12 for 5 Gb/s, 8.5Gb/s and 10Gb/s PRBS31 inputs, respectively. The chip dissipates 130 mW from a 1.2V power supply, while occupying an active area of 0.34 mm2.