Mong Song Liang

Generalized Interconnect Delay Time and Crosstalk Models: I. Applications of Interconnect Optimization Design

New analytical models for estimating the delay time of single line and coupled interconnect for ramp input waveform are derived. The accuracy of the signal delay time and crosstalk noise voltage models for various driver resistances, loading capacitances, and input-ramping rates has also been verified by simulation program with integrated circuit emphasis (SPICE) simulation. Based on the delay and crosstalk models, interconnect optimization design can be discussed thoroughly. The proposed guaranteed-performance interconnect design method is also discussed. These models are useful for performance estimation and layout optimization in VLSI synthesis as well as process optimization in technology development.

Impact of Hydrogenating Plasma Induced Oxide Charging Effects on the Characteristics of Polysilicon Thin Film Transistors

The impact of electrostatic charging damage on the characteristics and gate oxide integrity of polysilicon thin film transistors (TFTs) during plasma hydrogenation were investigated. Hydrogen atoms passivate trap states in the polysilicon channel; however, plasma processing induced electrostatic charging effects damage the gate oxide and the oxide/channel interface. The passivation effect of hydrogen atoms is antagonized by the generation of interface states. TFTs with different areas of antennas were used to study the damage caused by electrostatic fields. Oxide charging damage during plasma hydrogenation also seriously degrades the integrity of the gate oxide and the channel/oxide interface.

Rapid thermal annealing on the characteristics of polysilicon thin-film transistors in practical TFT SRAM process

In the practical thin-film transistor (TFT) SRAM process, the rapid thermal contact annealing (RTA) would seriously deteriorate the subthreshold characteristics of TFTs but it can improve the maximum transconductance. We suggest that these degradations are due to the generation of the deep states and we find these degradations can be recovered by a low-temperature anneal in H/sub 2//N/sub 2/ gas ambient.

Generalized Interconnect Delay Time and Crosstalk Models: II. Crosstalk-Induced Delay Time Deterioration and Worst Crosstalk Models

New analytical models for estimating crosstalk-induced delay time deterioration and the worst crosstalk models of a coupled interconnect for ramp input waveform are derived. The accuracy of these compact models at various driver resistances, loading capacitances, and input-ramping rates is verified by simulation program with integrated circuit emphasis (SPICE) simulation for the parallel interconnect system. The effects of crosstalk noise on the delay time at various ramp input rise times, for both simultaneous and non-simultaneous switching cases, are discussed here. In this study we show that crosstalk noise will be a limiting factor for future fast transition signals. The results reported herein are useful in the studies of delay time uncertainties due to noise and the interconnect worst-case design.

High performance polysilicon thin film transistors by H2O plasma hydrogenation

Abstract In this work, we report an efficient way to improve characteristics of polysilicon thin film transistors (TFTs). A TFT treated with H2O microwave plasma shows an excellent subthreshold swing of 130 mV DEC−1 and a threshold voltage of 2.2 V while TFT treated with conventional H2 radio frequency plasma shows an subthreshold swing of 200 mV DEC − 1 and a threshold voltage of 3.2 V. We also find that a TFT treated with H2O plasma also shows better interface strength under electric stress than a TFT treated with H2 plasma. The oxide integrity of a TFT with H2O plasma under constant current stress is also better than a TFT with H2 plasma.

Degradation of Flash Memory Using Drain-Avalanche Hot Electron (DAHE) Self-Convergence Operation Scheme

In this paper, the n-channel Flash memory device degradation by utilizing the drain-avalanche hot electron (DAHE) self-convergence (S-C) scheme is demonstrated for the first time. The injected hole originated by the channel electron induced avalanche hot hole generation is believed to be responsible for this degradation. This hole injection phenomena not only result in the interface state generation but also lead to the hole trapping in the tunnel oxide. The increased interface states degrade the conduction of the channel current severely, which leads to abnormal write/erase (W/E) endurance characteristics. The trapped holes in the tunnel oxide increase the tunneling probability and cause the gate disturbance issue. From the concerns of long term reliability, the self-convergence operation by utilizing the DAHE mechanism is not a proper scheme for reliable Flash memory products.

The Impacts of Back-End High Temperature Thermal Treatments on the Characteristics and Gate Oxide Reliability of Thin Film Transistor in Ultra Large Scale Integrated Circuit Process

The impacts of the two major high temperature treatments on the characteristics of thin film transistors (TFTs) in the back-end process of ultra large scale integrated circuit (ULSI) technology have been investigated. TFTs without any high temperature treatment show poor characteristics. High temperature furnace annealing and rapid thermal annealing (RTA) which are performed for boron phosphorous tetra ethyl ortho silicate (BPTEOS) planarization can improve the characteristics of low temperature recrystallized TFT. Then, the technologies used for contact annealing result significant difference on the characteristics of TFTs. High temperature furnace contact annealing can still greatly improve the characteristics of TFTs. However, after furnace annealing for BPTEOS planarization, RTA contact annealing deteriorates the characteristics of TFT. High temperature furnace annealing for BPTEOS planarization improves the charge to breakdown (Q bd) value of the gate oxide of TFT and so does the furnace contact annealing. However, RTA contact annealing performed after the furnace planarization flow deteriorates that of the gate oxide.